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PDF KAD5512P-50 Data sheet ( Hoja de datos )
| Número de pieza | KAD5512P-50 | |
| Descripción | 500MSPS A/D Converter | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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KAD5512P-50
®
www.DataSheet4U.com
Data Sheet
12-Bit, 500MSPS A/D Converter
General Description
The KAD5512P-50 is a low-power, high-performance, 12-bit,
500MSPS analog-to-digital converter designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process. The KAD5512P-50 is part of a
pin-compatible portfolio of 10, 12 and 14-bit A/Ds with
sample rates ranging from 125MSPS to 500MSPS.
The device utilizes two time-interleaved 12-bit, 250MSPS
A/D cores to achieve the ultimate sample rate of 500MSPS.
A single 500MHz conversion clock is presented to the
converter, and all interleave clocking is managed internally.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of matching
characteristics (gain, offset, skew) between the two
converter cores. These adjustments allow the user to
minimize spurs associated with the interleaving process.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P-50 is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
Pin-Compatible Family
MODEL
KAD5514P-25
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
KAD5512P-25, KAD5512HP-25
KAD5512P-21, KAD5512HP-21
KAD5512P-17, KAD5512HP-17
KAD5512P-12, KAD5512HP-12
KAD5510P-50
RESOLUTION
14
14
14
14
12
12
12
12
12
10
SPEED
(MSPS)
250
210
170
125
500
250
210
170
125
500
Ordering Information
PART NUMBER SPEED TEMP. RANGE PACKAGE PKG.
(Note)
(MSPS)
(°C)
(Pb-Free) DWG. #
KAD5512P-50Q72 500 -40 to +85 72 Ld QFN L72.10X10D
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
December 5, 2008
FN6805.0
Features
• Programmable Gain, Offset and Skew control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1 or ÷2
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
Applications
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
Key Specifications
• SNR = 64.0dBFS for fIN = 250MHz (-1dBFS)
• SFDR = 78dBc for fIN = 250MHz (-1dBFS)
• Power Consumption = 407mW
CLKP
CLKN
VINP
VINN
VCM
Clock Generation
&
Interleave Control
CLKOUTP
CLKOUTN
SHA
SHA
12-bit
250 MSPS
ADC
VREF
Digital
Error
Correction
12-bit
250 MSPS
ADC
VREF
1.25 V
+
–
SPI
Control
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
KAD5512P-50
Digital Specifications
PARAMETER
www.DataSheet4U.com
INPUTS
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT)
Input Current Low (OUTMODE,
NAP/SLP, CLKDIV, OUTFMT)
Input Capacitance
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
Timing Diagrams
SYMBOL
CONDITIONS
IIH
IIL
IIH
IIL
CDI
VT
VOS
tR
tF
VOH
VOL
tR
tF
VIN = 1.8V
VIN = 0V
3mA Mode
3mA Mode
IOH = -500µA
IOL = 1mA
Sample N
INP
INN
CLKN
CLKP
tA
tCPD
CLKOUTN
CLKOUTP
D[11:0]P
D[ 11:0]N
Latency = L Cycles
tDC
tPD
D a ta
N -L
D a ta
N - L +1
D ata
N-L+2
Data
N-L+3
D a ta
N - L +4
FIGURE 1. LVDS TIMING DIAGRAM
D ata
N
MIN TYP
01
-25 -12
15 25
-40 25
3
620
950 965
500
500
OVDD - 0.3
OVDD - 0.1
0.1
1.8
1.4
MAX
10
-5
40
-15
980
0.3
UNITS
µA
µA
µA
µA
pF
mVP-P
mV
ps
ps
V
V
ns
ns
Sample N
INP
INN
CLKN
CLKP
tA
t CPD
CLKOUTN
CLKOUTP
D[11:0]P
D[ 11:0]N
Latency = L Cycles
tD C
tPD
Data
N-L
D a ta
N - L +1
Dat a
N-L+ 2
Dat a
N-L+ 3
Dat a
N-L+ 4
FIGURE 2. CMOS TIMING DIAGRAM
D ata
N
5 FN6805.0
December 5, 2008
5 Page 
KAD5512P-50
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise
www.DataSheet4U.com
noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
(Continued)
0
Ain = -1. 0 dBFS
-20 SNR = 6 4. 6 d B FS
SFDR = 81. 3 d B c
SINAD = 64.5 dBFS
-40
0
A in = -1.0 dBFS
-20 S NR = 63. 9 d BFS
S FDR = 73. 9 dBc
S INA D = 6 3.5 dB FS
-40
-60 -60
-80 -80
-1 00 -1 00
-1 20
0
5 0 1 00 1 50 2 00
FR EQ U EN CY ( M Hz)
2 50
FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz
-1 20
0
5 0 1 00 1 50 2 00
FR EQ U EN CY ( M Hz)
2 50
FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz
0
A in = -1.0 dBFS
-20 S NR = 61. 8 d BFS
S FDR = 51. 7 dBc
S INA D = 5 1.7 dB FS
-40
-60
-80
-1 00
-1 20
0
5 0 1 00 1 50 2 00
FR EQ U EN CY ( M Hz)
2 50
FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz
0
-20 IM D = -90. 7dB FS
-40
-60
-80
-1 00
-1 20
0
5 0 1 00 1 50 2 00
FR EQ U EN CY ( M Hz)
2 50
FIGURE 19. SINGLE-TONE SPECTRUM @ 70MHz
0
-20 IMD = -8 3. 5dBFS
-40
-60
-80
-1 00
-1 20
0
50 100 150 200
FREQ UENCY ( M Hz)
2 50
FIGURE 20. TWO-TONE SPECTRUM @ 170MHz
11 FN6805.0
December 5, 2008
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet KAD5512P-50.PDF ] | |
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