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PDF AT24C64B Data sheet ( Hoja de datos )
| Número de pieza | AT24C64B | |
| Descripción | I2C-Compatible (2-Wire) Serial EEPROM | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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AT24C64B
I2C-Compatible (2-Wire) Serial EEPROM
64K (8192 x 8)
DATASHEET
Features
Low-voltage and Standard-voltage Operation
̶ 2.7V (VCC = 2.7V to 5.5V)
̶ 1.8V (VCC = 1.8V to 5.5V)
Low-power Devices (ISB = 6μA at 5.5V) Available
Internally Organized 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
400kHz Clock Rate
Write Protect Pin for Hardware Data Protection
32-byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5ms max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
8-lead JEDEC SOIC and TSSOP Packages
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT24C64B provides 65,536 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 8,192 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a
common 2-Wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are
essential. The AT24C64B is available in space saving 8-lead JEDEC SOIC and
8-lead TSSOP packages and is accessed via a 2-Wire serial interface. In addition,
the entire family is available in 2.7V (2.7 to 5.5V) and 1.8V (1.8 to 5.5V) versions.
Atmel-3350F-SEEPROM-AT24C64B-Datasheet_052014
1 page  
5.3 AC Characteristics
Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL
Gate and 100pF (unless otherwise noted). Test conditions are listed in Note 2.
1.8V to 3.6V
5V
Symbol
Parameter
Min Max Min Max Units
fSCL Clock Frequency, SCL
400 400 kHz
tLOW Clock Pulse Width Low
1.3 1.2
μs
tHIGH
Clock Pulse Width High
0.6 0.6
μs
tI Noise Suppression Time(1)
100 50 ns
tAA Clock Low to Data Out Valid
0.2 0.9 0.1 0.9
μs
tBUF Time the bus must be free before a new transmission can start(1) 1.3
1.2
μs
tHD.STA
Start Hold Time
0.6 0.6
μs
tSU.STA
Start Set-up Time
0.6 0.6
μs
tHD.DAT
Data In Hold Time
0 0 μs
tSU.DAT
Data In Set-up Time
100 100
ns
tR Inputs Rise Time(1)
0.3 0.3 μs
tF Inputs Fall Time(1)
300 300 ns
tSU.STO
Stop Set-up Time
0.6 0.6
μs
tDH Data Out Hold Time
200 50
ns
tWR Write Cycle Time
Endurance(1) 25C, Page Mode, 5.0V
Notes: 1. This parameter is characterized and is not 100% tested (TA = 25C).
2. AC measurement conditions:
RL (connects to VCC): 1.3k (2.5V, 5.5V), 10k (1.7V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5 x VCC
5
1,000,000
5 ms
Write
Cycles
AT24C64B [DATASHEET]
Atmel-3350F-SEEPROM-AT24C64B-Datasheet_052014
5
5 Page 
9. Read Operations
Read operations are initiated the same way as Write operations with the exception the Read/Write Select bit in
the device address word is set to one. There are three read operations:
Current Address Read
Random Address Read
Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during
the last Read or Write operation, incremented by one. This address stays valid between operations as long as
the device power is maintained. The address roll-over during Read is from the last byte of the last memory page
to the first byte of the first page. The address roll-over during Write is from the last byte of the current page to
the first byte of the same page.
Once the Device Address with the Read/Write Select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input zero but does generate a following Stop condition.
Figure 9-1. Current Address Read
S
T
A
R Device
T Address
R
E
A
D
SDA Line
M LRA
S S/C
B BWK
Data
S
T
O
P
N
O
A
C
K
Random Read: A Random Read requires a dummy Byte Write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another Start condition. The microcontroller now initiates a Current Address
Read by sending a Device Address with the Read/Write Select bit high. The EEPROM acknowledges the
Device Address and serially clocks out the data word. The microcontroller does not respond with a zero but
does generate a following Stop condition.
Figure 9-2. Random Read
SDA Line
S
T
A
R Device
T Address
W
R
I
T
E
M LR A
S S/ C
B BW K
1st, 2nd Word
Address (n)
S
T
A
R Device
T Address
A
C
K
Note:
Dummy Write
1. * = Don’t Care bits
R
E
A
D
A
C
K
Data (n)
S
T
O
P
N
O
A
C
K
AT24C64B [DATASHEET]
Atmel-3350F-SEEPROM-AT24C64B-Datasheet_052014
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AT24C64B.PDF ] | |
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