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PDF ACS8525 Data sheet ( Hoja de datos )
| Número de pieza | ACS8525 | |
| Descripción | Line Card Protection Switch | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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ACS8525 LC/P
Line Card Protection Switch for
SONET/SDH Systems
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Deswcwrwi.pDattiaoSnheet4U.com
Features
The ACS8525 is a highly integrated, single-chip solution
for “Hit-less” protection switching of SEC (SDH/SONET
Equipment Clock) + Sync clock “Groups”, from Master
and Slave SETS clock cards and a third (Stand-by) source,
for Line Cards in a SONET or SDH Network Element. The
ACS8525 has fast activity monitors on the SEC clock
inputs and will implement automatic system protection
switching against the Master clock failure. The selection
of the Master/Slave input can be forced by a Force Fast
Switch pin. If both the Master and Slave input clocks fail,
the Stand-by “Group” is selected or, if no Stand-by is
available, the device enters Digital Holdover mode.
The ACS8525 can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from a
backplane into a 155.52 MHz clock for local line cards.
Master and Slave SEC inputs to the device support
TTL/CMOS and PECL/LVDS. The Stand-by SEC and three
Sync inputs are TTL/CMOS only.
The ACS8525 generates two SEC clock outputs, via one
PECL/LVDS and one TTL/CMOS port, with spot
frequencies from 2 kHz up to 311.04 MHz (up to 155.52
MHz on the TTL/CMOS port). It also provides an 8 kHz
Frame Sync and a 2 kHz Multi-Frame Sync signal output
with programmable pulse width and polarity.
The ACS8525 includes a Serial Port, which can be SPI
compatible, providing access to the configuration and
status registers for device setup.
IEEE 1149.1 JTAG Boundary Scan is supported.
SONET/SDH applications up to OC-3/STM-1 bit rates
Switches between grouped inputs (SEC/Sync pairs)
Inputs: three SECs at any of 2, 4, 8 kHz (and N x 8 kHz
multiples up to 155.52 MHz), plus Frame Sync/Multi-
Frame Sync
Outputs: two SEC clocks at any of several spot
frequencies from 2 kHz up to 77.76 MHz via the
TTL/CMOS port and up to 311.04 MHz via the
PECL/LVDS port
Selectable clock I/O port technologies
Modes for E3/DS3 and multiple E1/DS1 rate output
clocks
Frequency translation of SEC input clock to a different
local line card clock
Robust input clock source activity monitoring on all
inputs
Supports Free-run, Locked and Digital Holdover
modes of operation
Automatic “Hit-less” source switchover on loss of
input
External force fast switch between SEC1/SEC2 inputs
Phase Build-out for output clock phase continuity
during input switchover
PLL “Locked” and “Acquisition” bandwidths
individually selectable from 18, 35 or 70 Hz
Serial interface for device set-up
Single 3.3 V operation, 5 V I/O compatible
Operating temperature (ambient) of -40 to +85°C
Available in LQFP 64 package
Block Diagram
Lead (Pb)-free version available (ACS8525T), RoHS
and WEEE compliant
Figure 1 Block Diagram of the ACS8525 LC/P
3 x SEC/Sync Input Groups
SEC1 & SEC2:
TTL/PECL/LVDS,
SEC3 and all Syncs
TTL only
SEC1
Master
SYNC1
Slave
SEC2
SYNC2
SEC3
Stand-by
SYNC3
Input
SEC Port
Monitors
and
Input
Selection
Control
Selector
DPLL1
DPLL2
Digital Feedback
APLL3
E1/DS1
Synthesis
SEC Inputs:
Programmable
Frequencies
2 kHz, 4 kHz,
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
TCXO or
XO
Priority Register Set
Table
MUX
2
MUX
1
APLL2
APLL 1
Output
Port
Frequency
Selection
Serial Interface
Port
SEC Outputs:
01 (PECL/LVDS)
02 (TTL)
Sync Outputs:
MFrSync 2 kHz (TTL)
FrSync 8 kHz (TTL)
01 and 02:
E1/DS1 (2.048/1.544 MHz)
and frequency multiples:
1.5x, 2x, 3x, 4x, 6x, 12x,
16x, and 24x E1/DS1
E3/DS3, 2 kHz, 8 kHz.
and OC-N* rates: OC-1 51.84 MHz
OC-3 155.52 MHz and derivatives:
6.48 MHz (O2 port only)
19.44 MHz, 25.92 MHz,
38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz (01 port only)
311.04 MHz (01 port only)
F8525D_001BLOCKDIA_05
Revision 3.01/August 2005 © Semtech Corp.
Page 1
www.semtech.com
1 page  
ACS8525 LC/P
ADVANCED COMMUNICATIONS
PinwDwwe.DsactarSipheteito4Un.com
Table 1 Power Pins
Pin Number
8, 9,
12
22
Symbol
VD1+, VD2+,
VD3+
VDD_DIFF
I/O
P
P
Type
-
-
27 VDD5V
P
-
32, 36,
38, 39,
45, 46,
54
4
14, 57
15, 58
7, 10,
11
31, 40,
53
21
1, 3
VDD1, VDD2,
VDD3, VDD4,
VDD5, VDD6,
VDD7
VA1+
P
P
VA2+, VA3+
P
AGND3, AGND4
DGND1, DGND2,
DGND3
DGND4, DGND5,
DGND6
GND_DIFF
AGND1, AGND2
P
P
P
P
-
-
-
-
-
-
-
-
FINAL
DATASHEET
Description
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts
±10%.
Supply Voltage: Digital supply for differential output pins 19 and 20,
+3.3 Volts ±10%.
Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts
(±10%) for clamping to +5 Volts. Connect to VDD for clamping to
+3.3 Volts. Leave floating for no clamping. Input pins tolerant up to
+5.5 Volts.
Supply Voltage: Digital supply to logic, +3.3 Volts ±10%.
Supply Voltage: Analog supply to clock multiplying PLL,
+3.3 Volts ±10%.
Supply Voltage: Analog supply to output PLLs APLL2 and APPL1,
+3.3 Volts ±10%.
Supply Ground: Analog ground for output PLLs APLL2 and APPL1.
Supply Ground: Digital ground for components in PLLs.
Supply Ground: Digital ground for logic.
Supply Ground: Digital ground for differential ports.
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Internally Connected
Pin Number
Symbol
2, 16, 60, 61, IC1, IC2, IC3, IC4,
62, 63
IC5, IC6,
55, 59
NC1, NC2
I/O
-
-
Type
-
-
Description
Internally Connected: Leave to float.
Not Connected: Leave to float.
Table 3 Other Pins
Pin Number
5
6
Symbol
INTREQ
REFCLK
13 SRCSW
I/O
O
I
I
Type
TTL/CMOS
TTL
TTLD
Description
Interrupt Request: Active High/Low software Interrupt output.
Reference Clock: 12.800 MHz (refer to section headed Local Oscillator
Clock).
Source Switching: Force Fast Source Switching on SEC1 and SEC2.
Revision 3.01/August 2005 © Semtech Corp.
Page 5
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5 Page 
ACS8525 LC/P
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Disquwwawlif.DicaatatSiohneeot4fUa.cnomon-selected SEC is based on
inactivity noted by the Activity Monitors. The currently
selected SEC can be disqualified for being out-of phase,
The default setting is shown in the following:
[21 x (8 - 4)] /8 = 1.0 secs
inactive, or if the source is outside the DPLL lock range. Fast Activity Monitor
If the currently selected SEC is disqualified, the next
highest priority qualified SEC is selected.
Interrupts for Activity Monitors
The loss of the currently selected SEC will eventually
cause the input to be considered invalid, triggering an
interrupt. The time taken to raise this interrupt is
dependant on the Leaky Bucket Configuration of the
activity monitors. The fastest Leaky Bucket setting will still
take up to 128 ms to trigger the interrupt. The interrupt
caused by the brief loss of the currently selected SEC is
provided to facilitate very fast source failure detection if
desired. It is triggered after missing just a couple of cycles
of the SEC. Some applications require the facility to switch
downstream devices based on the status of the SECs. In
order to provide extra flexibility, it is possible to flag the
main_ref_failed interrupt (Reg. 06 Bit 6) on the pin TDO.
This is simply a copy of the status bit in the interrupt
register and is independent of the mask register settings.
The bit is reset by writing to the interrupt status register in
the normal way. This feature can be enabled and disabled
by writing to Reg. 48 Bit 6.
Anomalies on the selected clock have to be detected as
they occur and the PLL must be temporarily isolated until
the clock is once again pure. The SEC activity monitoring
process cannot be used for this because the high degree
of accuracy required dictates that the process be slow. To
achieve the immediacy required, the PLL requires an
alternative mechanism. The phase locked loop itself
contains a fast activity detector such that within
approximately two missing input clock cycles, a no-activity
flag is raised and the DPLL is frozen in Digital Holdover
mode. This flag can also be read as the DPLL1
main_ref_failed bit (from Reg. 06 sts_interrupts, Bit 6)
and can be set to indicate a phase lost state by enabling
Reg. 73, Bit 6. With the DPLL in Digital Holdover mode it
is isolated from further disturbances. If the input becomes
available again before the activity monitor rejection alarm
has been raised, then the DPLL will continue to lock to the
input, with little disturbance. In this scenario, with the
DPLL in the “locked” state, the DPLL uses “nearest edge
locking” mode (±180° capture) avoiding cycle slips or
glitches caused by trying to lock to an edge 360° away, as
would happen with traditional PLLs.
Leaky Bucket Timing
The time taken (in seconds) to raise an inactivity alarm on
an SEC that has previously been fully active (Leaky Bucket
empty) will be:
(cnfg_upper_threshold_n) / 8
where n is the number of the Leaky Bucket Configuration.
If an input is intermittently inactive then this time can be
longer. The default setting of cnfg_upper_threshold_n is
6, therefore the default time is 0.75 s.
The time taken (in seconds) to cancel the activity alarm on
a previously completely inactive SEC is calculated, for a
particular Leaky Bucket, as:
[2 (a) x (b - c)]/ 8
where:
a = cnfg_decay_rate_n
b = cnfg_Bucket_size_n
c = cnfg_lower_threshold_n
(where n = the number of the relevant Leaky
Bucket Configuration in each case).
Selector
This block has two main functions:
z Selection of the Input reference clock source via
Reg. 33 force_select_reference_source
z Forcing of the Operating mode of the device, via
Reg. 32 cnfg_operating_mode
Selection of Input SECs
Under normal operation, the input SECs are selected
automatically by an order of priority given in the Priority
Table. For special circumstances however, such as chip or
board testing, the selection may be forced by
configuration.
Automatic operation selects an SEC based on its
predefined priority and its current validity. A table is
maintained which lists all valid SECs in the order of
priority. This is initially downloaded into the ACS8525 via
the Serial interface by the Network Manager, and is
subsequently modified by the results of the ongoing
quality monitoring. In this way, when all the defined
Revision 3.01/August 2005 © Semtech Corp.
Page 11
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ACS8525.PDF ] | |
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