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PDF ACS8509 Data sheet ( Hoja de datos )
| Número de pieza | ACS8509 | |
| Descripción | Synchronous Equipment Timing Source | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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ACS8509 SETS
Synchronous Equipment Timing Source for
SONET or SDH Network Elements
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Deswcwrwi.pDattiaoSnheet4U.com
Features
The ACS8509 is a highly integrated, single-chip solution
for the Synchronous Equipment Timing Source (SETS)
function in a SONET or SDH Network Element. The device
generates SONET or SDH Equipment Clocks (SEC) and
Frame Synchronization clocks. The ACS8509 is fully
compliant with the required international specifications
and standards.
Suitable for Stratum 3E*, 3, 4E, 4 and SONET
Minimum Clock (SMC) or SONET/SDH Equipment
Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia specifications
Accepts four individual input reference clocks
Generates six output clocks
The device supports Free-run, Locked and Holdover
modes. It also supports all three types of reference clock
source: recovered line clock, PDH network, and node
synchronization. The ACS8509 generates independent
SEC and BITS/SSU clocks, an 8 kHz Frame
Synchronization clock and a 2 kHz Multi-Frame
Synchronization clock.
Supports Free-run, Locked and Holdover modes of
operation
Robust input clock source quality monitoring on all
inputs
Automatic “hit-less” source switchover on loss of input
Phase build-out for output clock phase continuity
during input switchover and mode transitions
Two ACS8509 devices can be used together in a Master/
Slave configuration mode allowing system protection
against a single ACS8509 failure.
A microprocessor port is incorporated, providing access to
the configuration and status registers for device setup
and monitoring.
The ACS8509 includes a choice of edge alignment for
8 kHz input, as well as a low jitter n x E1/DS1 output
mode. The User can choose between OCXO or TCXO to
define the Stratum and/or Holdover performance
required.
Block Diagram
Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, EPROM
Programmable wander and jitter tracking attenuation
0.1 Hz to 20 Hz
Support for Master/Slave device configuration
alignment and hot/standby redundancy
IEEE 1149.1 JTAG Boundary Scan
Single +3.3 V operation, +5 V I/O compatible
Operating temperature (ambient) -40°C to +85°C
Available in 100 pin LQFP package.
Lead (Pb)-free version available (ACS8509T), RoHS
and WEEE compliant.
Note...* Meets holdover requirements, lowest bandwidth 0.1 Hz.
Figure 1 Block Diagram of the ACS8509 SETS
4 x TTL
Programmable;
2 kHz
4 kHz
N x 8 kHz
1.544/2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Input
Port
Monitors
and
Selection
Control
4 x SEC
T4 DPLL/Freq. Synthesis
TOUT4
Selector
Divider
PFD
Digital
Loop
Filter
DTO
T0 DPLL/Freq. Synthesis
TOUT0
Selecor
Divider
PFD
Digital
Loop
Filter
DTO
6x
Output
Ports
T0 APLL
(output)
Frequency
Dividers
Programmable Outputs:
01 (PECL (default)/LVDS) =
Programmable: 19.44 MHz (default),
51.84 MHz (OC-1), 77.76 MHz and
155.52 MHz (OC-3)
02 (TTL/CMOS) = 6.48 MHz (default)
19.44 MHz and 25.92 MHz,
and E1/DS1 multiples:
1 x, 2 x, 4 x, 8 x (1.544/2.048 MHz)
03 (TTL/CMOS) = 19.44 MHz (fixed)
04 (TTL/CMOS) =
1.544 MHz/2.048 MHz (E1/DS1)
FrSync (TTL/CMOS) =
8 kHz Frame Sync,
Fixed 50:50 MSR
MFrSync (TTL/CMOS) =
2 kHz Multiframe Sync,
Fixed 50:50 MSR
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1
JTAG
Chip
Clock
Generator
Priority Register Set
Table
Microprocessor
Port
F85509 001BLOCKDIA 01
OCXO or
TCXO
Revision 2.00/January 2006 © Semtech Corp.
Page 1
www.semtech.com
1 page  
ACS8509 SETS
ADVANCED COMMUNICATIONS
PinwDwwe.DsactarSipheteito4Un.com
Table 1 Power Pins
Pin Number
Symbol
12, 13, 16 VD+
33, 39
VDD_DIFF
44 VDD5
I/O
P
P
P
Type
-
-
-
50, 61, 85,
86 91
6
19
11, 14, 15,
24, 25, 29,
49, 62, 84,
87,92
32,
38
1, 5,
20
VDD
VA1+
VA2+
DGND
GND_DIFF
AGND
P
P
P
P
P
P
-
-
-
-
-
-
FINAL
DATASHEET
Description
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ±10%.
Supply Voltage: Digital supply for differential ports, +3.3 Volts ±10%.
Digital Supply for +5 Volts Tolerance to Input Pins. Connect to +5 Volts
(±10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3
Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts.
Supply Voltage: Digital supply to logic, +3.3 Volts ±10%.
Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ±10%.
Supply Voltage: Analog supply to output PLLs, +3.3 Volts ±10%.
Supply Ground: Digital ground for logic
Supply Ground: Digital ground for differential ports.
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Not Connected or Internally Connected Pins
Pin Number
Symbol
I/O
Type
Description
4, 17, 26
NC
3, 18, 22, 27,
28, 34, 35,
40, 41, 42,
43, 46, 47,
52, 53, 55,
57, 89, 93,
94, 96, 97, 98
IC
NC - Not connected: Leave to Float
IC - Internally Connected: Leave to Float.
Table 3 Other Pins
Pin Number
Symbol
2 TRST
I/O
I
7 TMS
I
Type
TTLD
TTLU
Description
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.
TRST = 0 for Boundary Scan stand-by mode, still allowing correct device
operation. If not used connect to GND or leave floating.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of
TCK. If not used connect to VDD or leave floating.
Revision 2.00/January 2006 © Semtech Corp.
Page 5
www.semtech.com
5 Page 
ACS8509 SETS
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
the frwewqwu.DeantacSyhoeuett4sUid.ceomthe hold-in range for long enough to
be detected, whilst the signal will also be rejected if the
eye closes sufficiently to affect the signal purity). The
“8klock” mode should be engaged for high jitter tolerance
according to these masks. All reference clock ports are
monitored for quality, including frequency offset and
general activity. Single short-term interruptions in
selected reference clocks may not cause
rearrangements, whilst longer interruptions, or multiple,
short-term interruptions, will cause rearrangements, as
will frequency offsets which are sufficiently large or
sufficiently long to cause loss-of-lock in the phase-locked
loop. The failed reference source will be removed from the
priority table and declared as unserviceable, until its
perceived quality has been restored to an acceptable
The registers sts_curr_inc_offset (address 0C, 0D, 07)
report the frequency of the DPLL with respect to the
external TCXO frequency. This is a 19-bit signed number
with one LSB representing 0.0003 ppm (range of
±80 ppm). Reading this regularly can show how the
currently locked source is varying in value e.g. due to
wander on its input.
The ACS8509 performs automatic frequency monitoring
with an acceptable input frequency offset range of
±16.6 ppm. The ACS8509 DPLL has a programmable
frequency limit of ±80 ppm. If the range is programmed to
be > 16.6 ppm, the frequency monitors should be
disabled so the input reference source is not
level.
automatically rejected as out of frequency range.
Table 7 Input Reference Source Jitter Tolerance
Jitter Tolerance
G.703
G.783
G.823
GR-1244-CORE
Frequency Monitor
Acceptance Range
±16.6 ppm
Frequency Acceptance
Range (Pull-in)
±4.6 ppm
(see Note (i))
±9.2 ppm
(see Note (ii))
Frequency Acceptance
Range (Hold-in)
±4.6 ppm
(see Note (i))
±9.2 ppm
(see Note (ii))
Frequency Acceptance
Range (Pull-out)
±4.6 ppm
(see Note (i))
±9.2 ppm
(see Note (ii))
Notes: (i) The frequency acceptance and generation range will be ±4.6 ppm around the required frequency when the external crystal
frequency accuracy is within a tolerance of ±4.6 ppm.
(ii) The fundamental acceptance range and generation range is ± 9.2 ppm with an exact external crystal frequency of 12.8 MHz. This is
the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps.
Revision 2.00/January 2006 © Semtech Corp.
Page 11
www.semtech.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ACS8509.PDF ] | |
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