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PDF ACS8514 Data sheet ( Hoja de datos )
| Número de pieza | ACS8514 | |
| Descripción | Synchronous Equipment Timing Source Partner IC | |
| Fabricantes | Semtech Corporation | |
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ADVANCED COMMS & SENSING
ACS8514 SETS Buddy
Synchronous Equipment Timing Source Partner IC for
2nd T4 DPLL, Accurate Monitoring & Input Extender
FINAL
DATASHEET
Description
The ACS8514 is an optional partner integrated circuit for
applications using the ACS8520/30. It adds an additional
BITS clock (T4 path) DPLL to a clock synchronization
system, for applications needing two T4 paths (e.g. to GR-253
figure 5-21).
An alternative use for this DPLL is as an input extender
such that the ACS8514 automatically selects one of 14
clock sources, its output then feeds the ACS8530/20
which can also select another 13 sources, giving a total
input selection range of 27 sources. An additional 13
sources can be added for each ACS8514 added.
An additional highly accurate phase and frequency monitor
is also available that can be used to carry out more
detailed analysis of standby clock reference sources. This
extra monitor is actually another DPLL which under
software control could be set to sequentially analyze each
input. It can check phase from 0.7º to 23000º and
frequency from 0.0003ppm to 80 ppm. An approximate
MTIE measurement could be calculated for each reference
input as an extra quality check.
Simultaneous activity and coarse frequency monitoring of
all input sources is performed in the same way as on the
ACS8520/30. These can be used to automatically qualify
and select sources for the extra T4 path or for input
selection for the ACS8520/30 when the ACS8514 is used
as an input extender.
Block Diagram
Figure 1 Block Diagram of the ACS8514 SETS Buddy
Features
♦ Partner to the ACS8520 & ACS8530 for use in SONET
Minimum Clock (SMC) or SONET/SDH Equipment Clock
(SEC) applications, to provide :
♦ One Extra independent T4 path for those systems being
designed to Figure 5-21 of Bellcore GR253[17],
♦ An additional DPLL for accurate phase, average phase,
frequency and average frequency measuring of any
clock source.
♦ Phase measurement accuracy to 0.7 degrees.
♦ Frequency measurement accuracy to 3x10-10
♦ Aids in enhancing Phase Build-out performance to
absorb phase disturbances when switching between
noisy input sources, via s/w control.
♦ Provides the facility to have long term frequency
measuring and averaging for BOTH the main and any
standby clock source so that the holdover frequency is
always accurate for both main and standby clock
selections.
♦ Accepts 14 individual input reference clocks, all with
robust input clock source quality monitoring.
♦ Microprocessor interface - Intel, Motorola, Serial,
Multiplexed, or boot from EPROM
♦ IEEE 1149.1[5] JTAG Boundary Scan
♦ Single 3.3 V operation. 5 V tolerant
♦ Lead (Pb)-free version available (ACS8514T),
RoHS and WEEE compliant
Revision 3.00 April 2007 © Semtech Corp.
Page 1
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1 page  
ACS8514 SETS Buddy
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ADVANCED COMMS & SENSING
FINAL
DATASHEET
Table 4 Other Pins
Pin Number
2
Symbol
TRST
I/O
I
7
8
9
10
21
23
24
25
27
28
40,
41
42,
43
46
47
48
51
52
53
54
55
56
57
58 - 60
63 - 69
TMS
INTREQ
TCK
REFCLK
TDO
TDI
I1
I2
TO2NEG
TO2POS
I5POS,
I5NEG
I6POS,
I6NEG
I3
I4
I7
I8
I9
I10
I11
I12
I13
I14
UPSEL(2:0)
A(6:0)
I
O
I
I
O
I
I
I
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
TTL D
TTL U
TTL/CMOS
TTL D
TTL
TTL/CMOS
TTL U
AMI
AMI
AMI
AMI
LVDS/PECL
PECL/LVDS
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
TTL D
Description
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan
mode. TRST = 0 for Boundary Scan stand-by mode, still allowing
correct device operation. If not used connect to GND or leave floating.
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising
edge of TCK. If not used connect to VDD or leave floating.
Interrupt Request: Active high/low software Interrupt output.
JTAG Clock: Boundary Scan clock input. If not used connect to GND or
leave floating.
Reference Clock: 12.8 MHz (refer to section headed Local Oscillator
Clock).
JTAG Output: Serial test data output. Updated on falling edge of TCK.
If not used leave floating.
JTAG Input: Serial test data Input. Sampled on rising edge of TCK. If
not used connect to VDD or leave floating.
Input reference 1: Composite clock 64 kHz + 8 kHz.
Input reference 2: Composite clock 64 kHz + 8 kHz.
Output reference 8: Composite clock, 64 kHz + 8 kHz negative pulse.
Output reference 8: Composite clock, 64 kHz + 8 kHz positive pulse.
Input reference 5: Programmable, default 19.44 MHz, default type
LVDS.
Input reference 6: Programmable, default 19.44 MHz, default type
PECL.
Input reference 3: Programmable, default 8 kHz.
Input reference 4: Programmable, default 8 kHz.
Input reference 7: Programmable, default 19.44 MHz.
Input reference 8: Programmable, default 19.44 MHz.
Input reference 9: Programmable, default 19.44 MHz.
Input reference 10: Programmable, default 19.44 MHz.
Input reference 11: Programmable, default (Master mode)
1.544/2.048 MHz, default (Slave mode) 6.48 MHz.
Input reference 12: Programmable, default 1.544/2.048 MHz.
Input reference 13: Programmable, default 1.544/2.048 MHz.
Input reference 14: Programmable, default 1.544/2.048 MHz.
Microprocessor select: Configures the interface for a particular
microprocessor type at reset.
Microprocessor Interface Address: Address bus for the
microprocessor interface registers. A(0) is SDI in Serial mode - output
in EPROM mode only.
Revision 3.00 April 2007 © Semtech Corp.
Page 5
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5 Page 
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ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
occur sufficiently close together, or by defect events which
occur in bursts. Events which are sufficiently spread out
should not trigger the alarm. By adjusting the alarm
setting threshold, the point at which the alarm is triggered
can be controlled. The point at which the alarm is cleared
depends upon the decay rate and the alarm clearing
threshold.
On the alarm setting side, if several events occur close
together, each event adds to the amplitude and the alarm
will be triggered quickly; if events occur a little more
spread out, but still sufficiently close together to overcome
the decay, the alarm will be triggered eventually. If events
occur at a rate which is not sufficient to overcome the
decay, the alarm will not be triggered. On the alarm
clearing side, if no defect events occur for a sufficient
time, the amplitude will decay gradually and the alarm will
be cleared when the amplitude falls below the alarm
clearing threshold. The ability to decay the amplitude over
time allows the importance of defect events to be reduced
as time passes by. This means that, in the case of isolated
events, the alarm will not be set, whereas, once the alarm
becomes set, it will be held on until normal operation has
persisted for a suitable time (but if the operation is still
erratic, the alarm will remain set). See Figure 3 .
There is one Leaky Bucket Accumulator per input channel.
Each Leaky Bucket can select from one of four Configurations
(Leaky Bucket Configuration 0 to 3). Each Leaky Bucket
Configuration is programmable for size, alarm set and
reset thresholds, and decay rate.
Figure 3 Inactivity and Irregularity Monitoring
Each source is monitored over a 128 ms period. If, within
a 128 ms period, an irregularity occurs that is not deemed
to be due to allowable jitter/wander, then the Accumulator
is incremented. Irregularity is defined as too much or too
little activity (corresponding to +/- 1000ppm on a
frequency basis).
The Accumulator will continue to increment up to the point
that it reaches the programmed Bucket size. The "fill rate"
of the Leaky Bucket is, therefore, 8 units/second. The
"leak rate" of the Leaky Bucket is programmable to be in
multiples of the fill rate (x 1, x 0.5, x 0.25 and x 0.125) to
give a programmable leak rate from 8 units/sec down to 1
unit/sec. A conflict between trying to "leak" at the same
time as a "fill" is avoided by preventing a leak when a fill
event occurs.
Disqualification of a non-selected reference source is
based on inactivity, or on an out-of-band result from the
frequency monitors. The currently selected reference
source can be disqualified for phase, frequency, inactivity
or if the source is outside the DPLL lock range. If the
currently selected reference source is disqualified, the
next highest priority, qualified reference source is
selected.
To avoid the DPLL being pulled off by clock inactivity on a
shorter timescale than 128ms, the DPLL contains a fast
activity detector such that within approximately two
missing input clock cycles, a no-activity flag is raised and
the DPLL is frozen in holdover mode, holding the last
output frequency value. With the DPLL in holdover mode it
is isolated from further disturbances. If the input
Revision 3.00 April 2007 © Semtech Corp.
Page 11
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| PDF Descargar | [ Datasheet ACS8514.PDF ] | |
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