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PDF TC35273 Data sheet ( Hoja de datos )
| Número de pieza | TC35273 | |
| Descripción | MPEG-4 Audiovisual LSI | |
| Fabricantes | Toshiba Semiconductor | |
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Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
TOSHIBA MPEG-4 Audiovisual LSI
TC35273
Tentative Technical Data Sheet
MPEG-4 Audiovisual LSI
Features
www.DataSheet4U.com
U
TC35273 is an MPEG-4 audiovisual codec LSI
which supports 3GPP 3G-324M video telephony
system. MPEG-4 video codec with QCIF (176x144
pixel) at 15 frames/s, AMR (Adaptive Multi Rate)
speech codec, and ITU-T H.223 are executed
concurrently at around 70MHz clock rate.
U Three signal processing units, an MPEG-4 video
codec, a speech codec / audio decoder, and a
multiplex / demultiplex unit, are integrated on a
P-FBGA201-1515-0.80A5
single chip.
U A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing
units. The embedded DRAM helps to reduce power consumption without performance
degradation.
U Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware
accelerators so as to bring programmability, high performance and low power consumption.
U Firmware programs for the RISCs are downloaded into the embedded DRAM before starting
operation. Various applications are performed by choosing an appropriate firmware.
U General host interface are adopted in order to support various host CPU.
U 2.5x to 6x of PLL is integrated on the chip for easy system integration.
• TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the
responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a
malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing
your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent
products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor
Reliability Handbook.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is
assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of
TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
TOSHIBA Confidential
1/23
2000-4-27
Version 0.90
1 page  
2. Terminals
2.1 Pin Assignment
TBD
2.2 Pin Allocation
TBD
2.3 I/O Pins
Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
www.DataSheet4U.com
PLL Pins
PLLFN
PLLDIV
PLLBP
PLLAVD
PLLAVS
3
Host
Interface
/HCS
/HWR
/HRD
HADDR
HDAT
/HWAIT
/HACK
HINT
7
16
Network
Interface
NWCLK
/NWOEN
NWDO
/NWIEN
NWDI
NWIFS
NWOFS
Test Pins
TGCLK
TSMODE
TDBISTEN
TDTMB
TDTCLK
TREOUT
TEST0-3
4
/RESET
STANDBY
VGSCLK
VGSADIO
VGSBDO
Video
General
Interface
TC35273
CAMCLK
CAMHREF
CAMVREF
CAMFSEL
8 CAMPIXEL
Camera
Interface
MPEG-4
Audiovisual
LSI
DISPCLK
DISPHSYNC
DISPYSYNC
DISPBLK
Display
Interface
8 DISPPIXEL
ADIMCLK
ADOMCLK
ADLRCLK
ADSCLK
ADSDO
Audio
PCM
Interface
ADSDI
5 ADCMD
Audio
ADC&DAC
Control
Fig. 2 Pin Map
TOSHIBA Confidential
5/23
Version 0.90
2000-4-27
5 Page 
Preliminary
MPEG-4 Audiovisual Codec LSI
TC35273
/HCS
HADDR
www.DataSheet4U.com
/HWR
/HWAIT
HDAT
(a)
TCSS
TADS
TWTAD
TWTID
TDTWS
(b) (c)
TCSH
TADH
TRDH
TRR
TDTID
Fig. 4 Write Operation in handshake mode
3.1.2 Synchronized access mode
In this mode, a host CPU accomplishes an access to TC35273 in the specified period without a
handshake. However, when the host CPU accesses to the embedded DRAM in TC35273, it has to
check whether the next access is available or not by checking a status register before the access.
Fig.5 shows the timing diagram of a read operation. A read access starts by asserting both a chip
select signal (/HCS) and a read signal (/RD) (timing (a)). After the specified cycles indicated as Tacs,
the host CPU gets the read data and finishes the read operation by negating both /HCS and /HRD
(timing (b)).
Fig.6 shows the timing diagram of a write operation. A write access starts by asserting both /HCS
and a write signal (/WR) (timing (a)). After the specified cycles, the host CPU finishes the write
operation by negating both /HCS and /HWR (timing (b)).
TOSHIBA Confidential
11/23
Version 0.90
2000-4-27
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet TC35273.PDF ] | |
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