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PDF HV9982 Data sheet ( Hoja de datos )
| Número de pieza | HV9982 | |
| Descripción | Switch Mode LED Driver IC | |
| Fabricantes | Supertex | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HV9982 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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HV9982
Three-Channel, Closed-Loop, Switch Mode LED Driver IC
Features
► Switch mode controller for single-switch converters
► Closed loop control of output current
♦ Buck
♦ Boost
♦ SEPIC
► High PWM dimming ratio
► Internal 40V linear regulator
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► Constant frequency operation
► Programmable slope compensation
► Linear and PWM dimming
► +0.2A/-0.4A gate drives for the switching FETs
► Output short circuit protection
► Output over voltage protection
► Hiccup mode protection
► Analog control of PWM dimming
Applications
► RGB backlight applications
► Multiple string white LED driver applications
General Description
The HV9982 is a three-channel, closed loop, peak current
mode PWM controller for driving a constant output current.
It can be used for driving either RGB LEDs or multiple
channels of white LEDs.
The HV9982 includes a 40V linear regulator which provides
an 8.0V supply to power the IC. The switching frequencies
of the three converters are controlled by an external clock
signal. The channels operate at a switching frequency of
1/12th of the external clock frequency to minimize the input
current ripple. Each converter is driven by a peak current
mode controller with output current feedback.
The three output currents can be individually dimmed using
either linear or PWM dimming. The IC also includes three
disconnect FET drivers which enable high PWM dimming
ratios and also help to disconnect the input in case of an
output short circuit condition. HV9982 includes a hiccup
mode protection for both open LED and short circuit
condition with automatic recovery when the fault clears.
Typical Boost Application Circuit
VIN GATE1
VDD
VDD1
VDD2
VDD3
CS1
GND1
OVP1
FLT1
FDBK1
PWMD1
PWMD2
PWMD3
REF1
REF2
REF3
HV9982
GATE2
CS2
GND2
OVP2
FLT2
EN FDBK2
CLK
GND
COMP1
COMP2
COMP3
SKIP
S1
S2
GATE3
CS3
GND3
OVP3
FLT3
FDBK3
RAMP
1 page  
Internal Block Diagram
VIN EN
VDD
HV9982
CLK
BANDGAP
1/12
REF
CLK A
CLK B
CLK C
Linear
Regulator
UVLO
POR
Shared circuitry
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RAMP
PWMD1
FLT1
OVP1
RAMP
Generator
RAMP
REF
RAMP
+
-
RAMP
PWMD A
FC
+ OVD A
-
+
-
CLK A
S1 S2
Replicated for each channel
SQ
PWMD A
R
FC
Q
+ BLANKING
-
CLK A
PWMD A
SCD A
FD A
+
-
PWMD A
+
-
2
BLANKING
PWMD A
DIS
GATE1
CS1
REF1
FDBK1
COMP1
S1
S2
SKIP
S1
S2
POR
FDA
FDB
FDC
0.1V
+
-
Fault
5V
+
-
Shared circuitry
SQ
R
Fault
DIS
FC
HV9982
5
5 Page 
HV9982
Pin Description
Pin # Name Description
Power supply pin for channel 1. It can either be connected to the VDD pin or supplied with an external
1
VDD1
power supply. It must be bypassed with a low ESR capacitor to GND1 (at least 0.1μF). All VDD pins
(VDD, VDD1-3) must be connected together externally. An external supply (7V – 9V) can be con-
nected to these pins to power the IC if the internal regulator is not used.
Used to drive an external disconnect switch. The disconnect switch is used to protect the LEDs in case
2 FLT1 of fault conditions and also help to provide excellent PWM dimming response by disconnecting and
reconnecting the LEDs from the output capacitor during PWM dimming.
3 CS1
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Used to sense the source current of the external power FET used with channel 1. It includes a built-in
100ns (min) blanking timer. An R-C network at this pin programs the slope compensation. Refer to the
Slope Compensation section for additional information.
4
COMP1
Stable closed loop control for channel 1 can be accomplished by connecting a compensation network
between each COMP1 pin and GND1.
5
FDBK1
Output current feedback input for channel 1. It receives a voltage signal from an external sense resis-
tor.
6
REF1
The voltage at this pin sets the output current level for channel 1. Recommended voltage range for
this pin is 0V – 1.25V.
Provides the over voltage protection for the channel 1. When the voltage at this pin exceeds 5.0V, the
7 OVP1 HV9982 is turned off and the fault timer starts. Upon completion of the fault timer the IC attempts to
restart.
8 VIN Input of the internal 40V linear regulator.
Output of the linear regulator. It maintains a regulated 7.75V as long as the voltage of the VIN pin is
9 VDD between 10V and 40V. It must be bypassed with a low ESR capacitor to GND (at least 0.1μF). Can be
used as a power supply for the three channels.
10 EN When pin is pulled below 0.8V, the IC goes into a standby mode and draws minimal current.
11 GND Ground connection for the common circuitry in the HV9982.
12
COMP2
Stable closed loop control for channel 2 can be accomplished by connecting a compensation network
between each COMP2 pin and GND2.
13
REF2
The voltage at this pin sets the output current level for channel 2. Recommended voltage range for
this pin is 0V – 1.25V.
Provides the over voltage protection for the channel 2. When the voltage at this pin exceeds 5.0V, the
14 OVP2 HV9982 is turned off and the fault timer starts. Upon completion of the fault timer the IC attempts to
restart.
15 SKIP Programs the hiccup timer for fault conditions. A capacitor to GND programs the hiccup time.
16
RAMP
Provides a ramp signal which is used while dimming the channels with pulse-width modulation with an
analog input. A capacitor to GND programs the PWM dimming frequency.
17 PWMD1 PWM dimming of the three channels is accomplished by using the PWMD pins. If S1 is LOW, then the
18
PWMD2
three pins directly control the PWM dimming of the three channels and a square wave input should be
applied at these pins. If S1 is high, then a 0V – 2.0V analog signal should be applied at these pins. The
19 PWMD3 PWM dimming is then done by comparing the analog voltage to the voltage at the RAMP pin.
20 S1 Digital input pins which select the operating mode of the PWMD inputs. Refer to the PWM dimming
21 S2 section for additional information.
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HV9982.PDF ] | |
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