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IDT - HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

Numéro de référence IDT70V631S
Description HIGH-SPEED 3.3V 256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
Fabricant IDT 
Logo IDT 





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IDT70V631S fiche technique
HIGH-SPEED 3.3V 256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
IDT70V631S
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12ns (max.)
Dual chip enables allow for depth expansion without
www.DataSheet4U.ecoxmternal logic
IDT70V631 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Functional Block Diagram
UBL
LBL
R/WL
CE0L
CE1L
BB
EE
01
LL
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 128-pin Thin Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
BB
EE
10
RR
UBR
LBR
R/WR
CE0 R
CE1 R
OEL
I/O0L- I/O17L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
256K x 18
MEMORY
ARRAY
Din_L
Din_R
OER
I/O0R - I/O17R
A17L
A0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A17R
A0R
BUSYL
SEML
INTL
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
TDI
TDO
JTAG
NOTES:
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2003 Integrated Device Technology, Inc.
1
OER
R/WR
CE0 R
CE1 R
TMS
TCK
TRST
BUSYR
SEMR
INTR
5622 drw 01
OCTOBER 2003
DSC-5622/5

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