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PDF KS1461 Data sheet ( Hoja de datos )

Número de pieza KS1461
Descripción RF Signal Processor
Fabricantes Samsung Semiconductor 
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PRELIMINARY
RF SIGNAL PROCESSOR
KS1461
INTRODUCTION
The KS1461 receives optical signals from the optical pickup and makes the data-generation RF
(Radio Frequency) signals needed in the system part, and the servo error signal and monitor signals, needed for
stable servo control. The modes to which this RF IC can be applied are the CD 1×, 2×, 4×, and 8× modes
(Wide PLL +/- 20%) and the DVD 1× and 2× CLV (Constant Linear Velocity) modes.
FEATURES
www.DataSheet4U.com
• Compatible to play back of CDs at 1×, 2×, 4×, or 8×, and DVDs at 1× and 2×
• Can deal with all of CD-R corresponding P/Us’ optical signal input without additional circuits
• Built-in PreAmp that correspond to various P/U unit and gain controllable
• Built-in AGC (Automatic Gain Control) circuit for intensity radiation detection feedback
• RF AMP & equalizer for CD 1×, 2×, 4×, 8× and DVD 1×, and 2× compatibility
• Astigmatism FE (Focus Error) AMP for CD and DVD built-in
• TE (Tracking Error) AMP built-in for 3-beam method of CD
• TE (Tracking Error) AMP built-in to the 1-beam DPD (Differential Phase Detector) for DVD
• RF mirror detection circuit built-in for CD and DVD
• RF defect detection circuit built-in for CD and DVD
• FOK (Focus O.K) signal detection circuit built-in for CD and DVD
• Built-in RF envelope signal generator circuit for CD and DVD
• Built-in ALPC (Automatic Laser Power Control) circuit for CD and DVD
• Built-in standard voltage generating circuit for analog circuit
• Built-in detection circuit for abnormal wave forms
• Built-in Auto Offset compensation circuit
• Range of power in operation: 4.5 ~ 5.5V
• 100 PIN, TQFP (0.5 mm PITCH)
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KS1461 pdf
PRELIMINARY
RF SIGNAL PROCESSOR
KS1461
Pin
No.
Pin Name
59 TE3OFST
60 DPDEQ1
61 DPDEQ2
62 FAULTOUT
63 DPDMUTE
www.DataSheet644U.comPLLCTL
65 TE1RES
66 DPDGND
67 VREFDPD
68 RREFDLY
69 DATA
70 CLOCK
71 STB
72 OSC
73 RESET
74 BCAI
75 BCAO
76 RFCT
77 CB2
78 CP2
79 RFRP
80 RFRPN
81 MROFST
82 CB1
83 CP1
84 MIRRI
85 EQVCC
86 RFEQ0
87 BCATH
88 EQIN
89 RFAGCO
90 AGCC
91 AGCI
Table 1. Pin Description
I/O
Description
Related Block
Related
Part
- Cap connection terminal (open) for 3B TE Offset
3B TE AMP
-
O DPD EQ (A+C) output terminal
DPD
-
O DPD EQ (B+D) output terminal
DPD
-
O DPD abnormal wave form output terminal (monitor)
DPD
-
I DPD TE MUTE control terminal (H: Mute)
DPD
MICOM
I DPD TE PLL variable input terminal
DPD
SERVO
I DPD TE PLL variable bias resistance
DPD
-
P Power GND input terminal for DPD TE
DPD
-
O CAP connection terminal for DPD TE center voltage
DPD VC AMP -
- Bias resistance connection terminal for Delay Block
Delay Block
-
I Data input terminal
Serial Interface MICOM
I Clock input terminal
Serial Interface MICOM
I Data Enable input terminal
Serial Interface MICOM
Input terminal for RC value of OSC, for Auto Offset Block
Auto OFSTCTL -
I Reset input terminal (L: Reset) for Auto Offset Block
Auto OFSTCTL MICOM
I BCA Filter1
BCA
-
O BCA Filter2
BCA
-
O RF Ripple Center voltage output terminal for Mirror
MIRROR
DSSP
- CAP connection terminal of RC value of Bottom Hold, for RFCT MIRROR
generation
- CAP connection terminal of RC value of Peak Hold, for RFCT gen- MIRROR
eration
O RF Ripple Amp output terminal for Mirror
MIRROR
-
-
DSSP
I Input terminal for selecting RFRP Amp gain
MIRROR
-
I RF Ripple Offset control terminal for Mirror
MRROR
-
- RC connection terminal of RC value of Bottom Hold, for RFRP
generation
MRROR
- RC connection terminal of RC value of Peak Hold, for RFRP gen- MRROR
eration
I Input terminal for MIRR signal generation
MRROR
-
-
-
P Power voltage input signal for RF EQ
RF EQ
-
0 RF EQ output terminal
RF EQ
PLL
I BCA Comparating Level control terminal
BCA
DSP
I RFAGCO input terminal for RF EQ
RFEQ,RFENV DSSP
O RF AGC AMP output terminal
RF AGC
-
- CAP connection terminal for time constant of AGC
RF AGC
-
I AGC voltage input terminal while in AGC hold
RF AGC
-
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KS1461 arduino
PRELIMINARY
RF SIGNAL PROCESSOR
KS1461
Table 2. Electrical Characteristics (Continued)
No Item
Symbol
Input
Measurement Min. Typ. Max. Unit
Point
81 Tracking Bal-
ance Adjust-
ment Range2
Vbalc2
82 Tracking Bal-
ance Adjust-
ment Range3
www.DataShee8t43U.cTormacking Bal-
ance Adjust-
ment Range4
Vbalc3
Vbalc4
84 Tracking Bal-
ance Adjust-
ment Range5
Vbalc5
85 Tracking Bal-
ance Adjust-
ment Range6
Vbalc6
86 Tracking
Balance
Adjustment
Accuracy
Vbalacc
87 Phase Compar- Vphlim1
ator Limit1
88 Vphlim2
89 Phase Compar- Vphlim3
ator Limit2
90 Vphlim4
91 Phase Compar- Vphlim5
ator Limit3
92 Vphlim6
93 Abnormal
Tflt1
Waveform
Detecting Cir-
cuit 1
(DVD 1X, PLL
= 2.5V)
(A,C) DVD: 250 mVpp 3.924MHz sine + Vc
(B,D DVD: 250mVPP 3.924MHz sine +Vc
TBAL: Step Variable
DVD 1X, PLL = 3.75V
TE
(A,C) DVD: 250 mVpp 1.308MHz sine + Vc
(B,D) DVD: 250mVPP 1.308MHz sine +Vc
TBAL: Step Variable
DVD 1X, PLL = 1.25V
TE
(A,C) DVD: 250 mVpp 5.232MHz sine + Vc
(B,D) DVD: 250mVPP 5.232MHz sine +Vc
TBAL: Step Variable
DVD 2X, PLL = 2.5V
TE
(A,C) DVD: 250 mVpp 7.848MHz sine + Vc
(B,D) DVD: 250mVPP 7.848MHz sine +Vc
TBAL: Step Variable
DVD 2X, PLL = 3.75V
TE
(A,C )DVD: 250 mVpp 2.616MHz sine + Vc
(B,D) DVD: 250mVPP 2.616MHz sine +Vc
TBAL: Step Variable
DVD 2X, PLL = 1.25V
TE
(A,C )DVD, (B,D) DVD: standard input according TE
to each speed & PLL voltage
TBAL: STEP variable,
DVD speed & PLL voltage is variable.
(A,C) DVD: Input1, Fin1=2MHz,
(B,D) DVD: Input2,
PD_LIMIT=90ns
TE
(A,C) DVD: Input1,
(B,D) DVD: Input2, Fin1 = 2MHz
PD_LIMIT = 90ns
TE
(A,C) DVD: Input1, Fin1=2MHz
(B,D) DVD: Input2,
PD_LIMIT = 60ns
TE
(A,C )DVD: Input1,
(B,D) DVD: Input2, Fin1=2MHz
PD_LIMIT = 60ns
TE
(A,C) DVD: Input1, Fin1 = 2MHz
(B,D) DVD: Input2,
PD_LIMIT = 30ns
TE
(A,C) DVD: Input1,
(B,D) DVD: Input2, Fin1 = 2MHz
PD_LIMIT = 30ns
(A,C) DVD: Input1, Fin1 = 200kHz
(B,D) DVD: Input2
Measuring the time from falling edge where only
(B,D) DVD exists, to when FAULTO goes “High”
(B,D) DVD
FAULTO
-1.2 1.2 V
-1.2 1.2 V
-1.2 1.2 V
-1.2 1.2 V
-1.2 1.2 V
10 mV
1.296 1.44 1.584 V
-1.584 -1.44 -1.296
0.864 0.96 1.056 V
-1.056 -0.96 -0.864
0.432 0.48 0.528 V
-0.528 -0.48 -0.432
-10% 611.6 +10% ns
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