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PDF S3C6410 Data sheet ( Hoja de datos )
| Número de pieza | S3C6410 | |
| Descripción | 32-Bit Risc Microcontroller | |
| Fabricantes | Samsung | |
| Logotipo |  |
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The Features of
S3C6410
S3C6400 vs. S3C6410
OCT 30, 2007
REV 0.2
C fid i l P i
fS
El i C L d
1 page  
S3C6400 VS S3C6410
HSMMC
IIC
HSMMC(Ver3.1)
(support SD Host Controller spec
Ver1.0)
HSMMC (Ver4.0)
(support SD Host Controller spec Ver2.0)
New SFRs added
1ch 2ch
UART
www.DataSheRetT4UC.com
IIS
TSADC
4ch 4ch (3Mbps)
Tick clock source is 32768Hz
Tick counter is 16bit
16bit I2S 2ea
10bit 8channel
Tick clock source
(32768/16384/8192/4096/2048/1024/512/256/1
28/64/32/16/8/4/2/1)
S/W compatible.
24bit Stereo I2S 2ea + 24bit Multi-
Channel(up to 5.1) I2S 1ea
Bit length setting /
Multi-Channel I2S
transmission setting
12bit 8channel
S/W compatible.
3D New
Note)
1. S/W change: User must change the software in S3C6410 even though user wants to use the same
function of S3C6400 (refer to respective chapter in detail)
2. If user would like to use new IP or function, it is necessary to change software
3. There is no software change except above items
C
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
5
5 Page 
S3C6400 VS S3C6410
HCLK_IROM
HCLK_DDR1
HCLK_DDR0
HCLK_MEM1
HCLK_MEM0
HCLK_USB
www.DataSheet4HUC.cLoKm_HSMMC2
HCLK_HSMMC1
HCLK_HSMMC0
HCLK_MDP
HCLK_DHOST
HCLK_IHOST
HCLK_DMA1
HCLK_DMA0
HCLK_JPEG
HCLK_CAMIF
HCLK_SCALER
HCLK_2D
HCLK_TV
RESERVED
HCLK_POST0
HCLK_ROT
HCLK_LCD
HCLK_TZIC
HCLK_INTC
HCLK_MFC
[25] Gating HCLK for IROM (0: mask, 1: pass)
[24] Gating HCLK for DDR1 (0: mask, 1: pass)
[23] Gating HCLK for DDR0 (0: mask, 1: pass)
[22] Gating HCLK for DMC1 (0: mask, 1: pass)
[21]
Gating HCLK for DMC0, SROM, OneNAND, NFCON,
CFCON (0: mask, 1: pass)
[20] Gating HCLK for USB OTG (0: mask, 1: pass)
[19] Gating HCLK for HSMMC2 (0: mask, 1: pass)
[18] Gating HCLK for HSMMC1 (0: mask, 1: pass)
[17] Gating HCLK for HSMMC0 (0: mask, 1: pass)
[16] Gating HCLK for MDP (0: mask, 1: pass)
[15] Gating HCLK for direct HOST interface (0: mask, 1: pass)
[14] Gating HCLK for indirect HOST interface (0: mask, 1: pass)
[13] Gating HCLK for DMA1 (0: mask, 1: pass)
[12] Gating HCLK for DMA0 (0: mask, 1: pass)
[11] Gating HCLK for JPEG (0: mask, 1: pass)
[10] Gating HCLK for camera interface (0: mask, 1: pass)
[9] Gating HCLK for scaler (0: mask, 1: pass)
[8] Gating HCLK for 2D (0: mask, 1: pass)
[7] Gating HCLK for TV encoder (0: mask, 1: pass)
[6] RESERVED
[5] Gating HCLK for POST0 (0: mask, 1: pass)
[4] Gating HCLK for rotator (0: mask, 1: pass)
[3] Gating HCLK for LCD controller (0: mask, 1: pass)
[2] Gating HCLK for trust interrupt controller (0: mask, 1: pass)
[1]
Gating HCLK for vectored interrupt controller (0: mask, 1:
pass)
[0] Gating HCLK for MFC (0: mask, 1: pass)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PCLK_GATE
RESERVED
PCLK_IIC1
PCLK_IIS2
RESERVED
PCLK_SKEY
PCLK_CHIPID
PCLK_SPI1
BIT DESCRIPTION
[31:28] RESERVED
[27] Gating PCLK for IIC1 (0: mask, 1: pass)
[26] Gating PCLK for IIS2 (0: mask, 1: pass)
[25] RESERVED
[24] Gating PCLK for security key (0: mask, 1: pass)
[23] Gating PCLK for chip ID (0: mask, 1: pass)
[22] Gating PCLK for SPI1 (0: mask, 1: pass)
RESET VALUE
0x1F
1
1
1
1
1
1
C
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet S3C6410.PDF ] | |
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