|
|
PDF R8A66174SP Data sheet ( Hoja de datos )
| Número de pieza | R8A66174SP | |
| Descripción | PARALLEL-IN SERIAL-OUT DATA BUFFER | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de R8A66174SP (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
|
No Preview Available !
R8A66174SP
PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO
REJ03F0278-0101
Rev. 1.01
Oct.06.2008
DESCRIPTION
The R8A66174 is a CMOS LSI with 63-byte FIFO (First-In First-Out Memory). The commands or up to 63-
bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by
executing command, and when the stored data is outputted all, R8A66174 will output an interrupt request
signal. R8A66174 has 2-bit output pins (/OE, LATCH) which can set/reset outside devices by the command,
R8A66174 can be connected to peripheral circuits that have a serial latch structure. R8A66174 is the
succession product of M66300.
FEATURES
www.DataSheet4U●.coGmeneral-purpose 8-bit CPU bus compatible
● Built-in 63-byte FIFO
● High-speed output (10Mbps)
● It’s able to connect to LED array driver such as R8A66160 or R8A66161 directly
● Low-noise, high-output circuit
IOL=16mA, IOH=-16mA (IOL=4mA, IOH=-4mA for /INT)
● Schmitt input (/RESET)
● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V)
● Wide operating temperature range (Ta=-40~85oC)
APPLICATION
General digital equipment for industrial and home use, panel display controllers, and eraser unit controller for
copying machine.
PIN CONFIGURATION (TOP VIEW)
WRITE INPUT
DATA BUS
WR
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 Vcc
19 C/D COMMAND/DATA INPUT
18 CS
CHIP SELECT INPUT
17 RESET RESET INPUT
16 INT INTERRUPT REQUEST OUTPUT
15 OE OUTPUT ENABLE OUTPUT
14 LATCH LATCH OUTPUT
13 SDATA SHIFT DATA OUTPUT
12 SCLK SHIFT CLOCK OUTPUT
11 Φ
CLOCK INPUT
REJ03F0278-0101 Rev.1.01 Oct.06.2008
Page 1 of 11
1 page  
R8A66174SP
www.DataSheet4U.com
1 Division ratio setting
When D7 = 1
Set/Reset
1 LATCH and /OE,
and cancel /INT
When D3 = 1
D6 D5 D4 Division ratio
0 0 0Φ
0 0 1 1/2 of Φ
0 1 0 1/4 of Φ
0 1 1 1/8 of Φ
1 0 0 1/16 of Φ
D2 D1
00
01
10
11
/OE
0
0
1
1
LATCH
0
1
0
1
When D7 = D3 = 0
D7 D6 D5 D4 D3 D2 D1 D0
D0 Mode setting
0 WRITE
1 SERIAL OUT
Fig. 2 Instruction set
REJ03F0278-0101 Rev.1.01 Oct.06.2008
Page 5 of 11
5 Page 
R8A66174SP
PACKAGE OUTLINE
Package
20pin SOP
RENESAS Code
PRSP0020DG-A
Previous Code
20P2X-C
www.DataSheet4U.com
All trademarks and registered trademarks are the property of their respective owners.
REJ03F0278-0101 Rev.1.01 Oct.06.2008
Page 11 of 11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet R8A66174SP.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| R8A66174SP | PARALLEL-IN SERIAL-OUT DATA BUFFER | Renesas Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |