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PDF KM681002C Data sheet ( Hoja de datos )
| Número de pieza | KM681002C | |
| Descripción | 128Kx8 Bit High-Speed CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KM681002C (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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PRELIMINARY
KM681002C/CL, KM681002CI/CLI
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating).
Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev.No.
History
Rev. 0.0
Initial release with Preliminary.
Rev. 1.0
www.DataSheet4U.com
Rev. 2.0
Release to Final Data Sheet.
1.1. Delete Preliminary.
2.2. Added Data Retention Characteristics.
Add 10ns part.
Draft Data
Aug. 5. 1998
Mar. 3. 1999
Remark
Preliminary
Final
Mar. 3. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
March 2000
1 page  
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
CMOS SRAM
WRITE CYCLE*
Parameter
KM681002C-10
Symbol
Min Max
KM681002C-12
Min Max
Write Cycle Time
tWC 10 - 12 -
Chip Select to End of Write tCW 7 - 8 -
Address Set-up Time
tAS 0 - 0 -
Address Valid to End of Write
tAW
7
-
8
-
Write Pulse Width(OE High)
tWP
7
-
8
-
Write Pulse Width(OE Low)
tWP1
10
-
12
-
Write Recovery Time
tWR 0 - 0 -
www.DataSheet4U.coWmrite to Output High-Z
tWHZ
0
5
0
6
Data to Write Time Overlap tDW 5 - 6 -
Data Hold from Write Time tDH 0 - 0 -
End Write to Output Low-Z tOW 3 - 3 -
* The above parameters are also guaranteed at industrial temperature range.
KM681002C-15
Min Max
15 -
9-
0-
9-
9-
15 -
0-
07
7-
0-
3-
KM681002C-20
Min Max
20 -
10 -
0-
10 -
10 -
20 -
0-
09
8-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
Data out
VCC
Current
ICC
ISB
tAA
tCO
tOE
tOLZ
tLZ(4,5)
tPU
50%
tRC
tHZ(3,4,5)
Valid Data
tOHZ
tOH
tPD
50%
-5-
Revision 2.0
March 2000
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KM681002C.PDF ] | |
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