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PDF KM681001A Data sheet ( Hoja de datos )
| Número de pieza | KM681001A | |
| Descripción | 128K x 8 Bit High-Speed CMOS Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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PRELIMINARY
KM681001A
CMOS SRAM
Document Title
128Kx8 High Speed Static RAM(5V Operating), Evolutionary Pin Out.
Operated at Commercial Temperature Range.
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
www.DataSheet4U.comRev. 2.0
Rev. 3.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary
Release to final Data Sheet.
2.1. Delete Preliminary
Update D.C and A.C parameters.
3.1. Update D.C parameters
Items
Previous spec.
(15/17/20ns part)
Icc 190/180/170mA
Isb 30mA
Isb1 10mA
3.2. Update A.C parameters
Items
Previous spec.
(15/17/20ns part)
tCW 12/12/13ns
tAW 12/12/13ns
tWP1(OE=H)
12/12/13ns
tDW 8/9/10ns
Updated spec.
(15/17/20ns part)
165/165/160mA
25mA
8mA
Updated spec.
(15/17/20ns part)
10/11/12ns
10/11/12ns
10/11/12ns
7/8/9ns
Draft Data
Jan. 18th, 1995
Apr. 22th, 1995
Remark
Design Target
Preliminary
Feb. 29th, 1996 Final
Jul. 16th, 1996
Final
Rev. 4.0
Rev. 5.0
Update D.C and A.C parameters and add 300mil-SOJ PKG.
4. 1. Add 32-Pin 300mil-SOJ Package.
4. 2. Update D.C and A.C parameters.
Items
Previous spec.
(15/17/20ns part)
Updated spec.
(15/17/20ns part)
Icc
165/165/160mA
125/125/120mA
tOW
3/4/5ns
3/3/3ns
4.3. Add the test condition for Voh1 with Vcc=5V±5% at 25°C
4.4. Add timing diagram to define tWP1 as ″(Timing Wave Form of
Write Cycle(OE=Low Fixed)″
5.1. Delete 17ns Part
5.2. Delete 32-SOJ-300 Package
Jun. 2nd, 1997
Final
Feb. 25th, 1998 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 5.0
February 1998
1 page  
KM681001A
WRITE CYCLE
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
www.DataSheet4U.com
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
NOTE: tWR=tWR1, tWR2
PRELIMINARY
CMOS SRAM
Symbol
tWC
tCW
tAS
tAW
tWP
tWP1
tWR*
tWHZ
tDW
tDH
tOW
KM681001A-15
Min Max
15 -
10 -
0-
10 -
10 -
15 -
0-
08
7-
0-
3-
KM681001A-20
Min Max
20 -
12 -
0-
12 -
12 -
20 -
0-
0 10
9-
0-
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
Address
Data Out
tOH
Previous Valid Data
tAA
tRC
Valid Data
-5-
Rev 5.0
February 1998
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet KM681001A.PDF ] | |
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