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PDF ICS839893I Data sheet ( Hoja de datos )
| Número de pieza | ICS839893I | |
| Descripción | 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
GENERAL DESCRIPTION
The ICS839893I is a high-performance one to
ICS thirteen LVCMOS/LVTTL buffer/divider and is
HiPerClockS™ a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
device has two selectable LVCMOS/LVTTL
clock inputs and it generates 13 new LVCMOS/LVTTL clock
outputs. The first bank of six outputs offers divide-by-1, 2, 4,
8 or 16. The second bank of six outputs can be configured to
w w w . D a t taheSshame e dt i4vidUe. rcatoiomas the first bank, or with an additional
divide-by-two. The first two banks can be placed into a high-
impedance output state with the assertion of a LOW on the
nOE/MR input. One additional output can be configured
to divide-by-4, 6, 8 or 16. This device is functional with full
3.3V or full 2.5V supplies.
FEATURES
• 13 LVCMOS/LVTTL outputs: 3 banks (6, 6, 1 outputs per
bank respectively)
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Output skew: 40ps (maximum), within bank
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free compliant
packages
SIMPLIFIED BLOCK DIAGRAM
nOE/MR
CLK0
CLK1
REF_SEL
0
1
FSEL[0:2]
FSEL3
FFSSEELL00 FFSSELE1L1 FSFESLE2 L2QAQA
0 0 0 ÷1
0 0 0 ÷1
0 0 1 ÷2
0 1 0 ÷2
0 1 1 ÷4
1 0 0 ÷2
1 0 1 ÷16
1 1 0 ÷8
1 1 1 ÷4
0
÷2 1
FSEL0 FSEL1 FSEL2 QC
0 0 0 ÷8
0 0 1 ÷8
0 1 0 ÷6
0 1 1 ÷8
1 0 0 ÷4
1 0 1 ÷16
1 1 0 ÷8
1 1 1 ÷4
DQ
DQ
DQ
PIN ASSIGNMENT
GND
QA0:QA5 QA0
QA1
VDDO_A
GND
QA2
QB0:QB5 QA3
VDDO_A
GND
QA4
QA5
QC VDDO_A
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 ICS839893I 21
41 48-Pin LQFP 20
42 7mm x 7mm x 1.4mm 19
43 body package 18
44 17
45 Y Package 16
46 Top View 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
GND
QB0
QB1
VDDO_B
GND
QB2
QB3
VDDO_B
GND
QB4
QB5
VDDO_B
839893AYI
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 8, 2005
1 page  
Integrated
Circuit
Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE
4C.
LVCMOS/LVTTL
DC
CHARACTERISTICS,
V
DD
=
V
DDO_A
=
V
DDO_B
=
V
DDO_C
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V
IH
VIL
IIH
www.DataSheet4IIUL .com
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK0, CLK1,
nOE/MR, REF_SEL
FSEL0:FSEL3
CLK0, CLK1,
nOE/MR, REF_SEL
FSEL0:FSEL3
V = 3.3V
DD
VDD = 3.3V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
2
-0.3
-5
V + 0.3
DD
0.8
200
V Output High Voltage; NOTE 1
OH
2.6
VOL Output Low Voltage; NOTE 1
Note 1: Outputs terminated with 50Ω to VDDO_x/2. See Parameter Measurement Information,
3.3V Output Load Test Circuit diagram.
0.5
Units
V
V
µA
µA
V
V
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V Input High Voltage
IH
1.7
VIL Input Low Voltage
CLK0, CLK1,
-0.3
IIH
Input High Current nOE/MR, REF_SEL
VDD = VIN = 2.625V
FSEL0:FSEL3
CLK0, CLK1,
IIL
Input Low Current nOE/MR, REF_SEL
VDD = 2.625V, VIN = 0V
-5
FSEL0:FSEL3
V + 0.3
DD
0.7
200
V Output High Voltage; NOTE 1
OH
1.8
VOL Output Low Voltage; NOTE 1
Note 1: Outputs terminated with 50Ω to VDDO_x/2. See Parameter Measurement Information,
2.5V Output Load Test Circuit diagram.
0.5
Units
V
V
µA
µA
V
V
839893AYI
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 8, 2005
5 Page | ||
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