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PDF ICS83947I Data sheet ( Hoja de datos )

Número de pieza ICS83947I
Descripción 1-TO-9 LVCMOS FANOUT BUFFER
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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Integrated
Circuit
Systems, Inc.
ICS83947I
LOW SKEW, 1-TO-9
LVCMOS FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
ICS
The ICS83947I is a low skew, 1-to-9 LVCMOS
Fanout Buffer and a member of the HiPerClockS™
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The low impedance LVCMOS/LVTTL out-
puts are designed to drive 50series or parallel
terminated transmission lines. The effective fanout can be in-
creased from 9 to 18 by utilizing the ability of the outputs to
drive two series terminated lines.
www.DataSheeGt4uUa.croamnteed output and part-to-part skew characteristics
make the ICS83947I ideal for high performance, single ended
applications that also require a limited output voltage.
9 LVCMOS/LVTTL outputs
Selectable CLK0 and CLK1 can accept the following
input levels: LVCMOS and LVTTL
Maximum output frequency: 110MHz
Output skew: 500ps (maximum)
Part-to-part skew: 2ns (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Lead-Free package available
Pin compatible with the MPC947
BLOCK DIAGRAM
CLK_EN
CLK0
CLK1
0
1
D
Q
LE
CLK_SEL
OE
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q0 GND 1
CLK_SEL 2
24 GND
23 Q3
Q1 CLK0 3
2 2 VDDO
Q2
CLK1 4
ICS83947I 21 Q4
CLK_EN 5
20 GND
Q3 OE 6
19 Q5
VDD 7
Q4
GND 8
1 8 VDDO
17 GND
Q5 9 10 11 12 13 14 15 16
Q6
Q7
Q8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
83947AYI
http://www.icst.com/products/hiperclocks.html
1
REV. B OCTOBER 11, 2004

1 page




ICS83947I pdf
Integrated
Circuit
Systems, Inc.
ICS83947I
LOW SKEW, 1-TO-9
LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V ± 0.15V
www.DataSheet4UV.cDDom
LVCMOS
GND
-1.65V ± 0.15V
SCOPE
Qx
V
DDO
Qx 2
V
DDO
Qy 2
t sk(o)
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
PART 1
Qx
PART 2
Qy
V
DDO
2
V
DDO
2
t sk(pp)
PART-TO-PART SKEW
0.8V
Clock
Outputs
2V
tR
OUTPUT RISE/FALL TIME
83947AYI
CLK0,
CLK1
Q0:Q8
VDD
2
VDDO
2
t
PD
PROPAGATION DELAY
2V
0.8V
tF
Q0:Q8
V
DDO
2
Pulse Width
t
PERIOD
odc = t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
http://www.icst.com/products/hiperclocks.html
REV. B OCTOBER 11, 2004
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