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PDF ICS83940I-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS83940I-01 | |
| Descripción | 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83940I-01 is a low skew, 1-to-18
ICS LVPECL-to-LVCMOS/LVTTL Fanout Buffer and a
HiPerClockS™ member of the HiPerClockS™family of High Per-
formance Clock Solutions from ICS. The
ICS83940I-01 has two selectable clock inputs.
The PCLK, nPCLK pair can accept LVPECL, CML or SSTL
input levels. The single ended clock input accepts LVCMOS
or LVTTL input levels. The low impedance LVCMOS/LVTTL
www.DataSheeot4uUtp.cuotms are designed to drive 50Ω series or parallel termi-
nated transmission lines. The effective fanout can be increased
from 18 to 36 by utilizing the ability of the outputs to drive two
series terminated lines.
The ICS83940I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes. Guar-
anteed output and part-to-part skew characteristics make the
ICS83940I-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
FEATURES
• 18 LVCMOS/LVTTL outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC940L in single supply
applications
BLOCK DIAGRAM
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
0
1
PIN ASSIGNMENT
18
Q0:Q17
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS83940I-01 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q6
Q7
Q8
VDDO
Q9
Q10
Q11
GND
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940DYI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 1, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions Minimum Typical
VIH
VIL
VPP
VCMR
Input High Voltage
LVCMOS_CLK
Input Low Voltage
LVCMOS_CLK
Peak-to-Peak Input Voltage PCLK, nPCLK
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK
2.4
300
VDD - 1.4
www.DataSheet4IIUN .com Input Current
VOH Output High Voltage
IOH = -20mA
1.8
VOL Output Low Voltage
IOL = 20mA
IDD Core Supply Current
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Maximum
VDD
0.8
1000
VDD - 0.6
±200
0.5
25
Units
V
V
mV
V
µA
V
V
mA
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Output Frequency
PCLK, nPCLK;
tpLH
Propagation Delay
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
tpLH
Propagation Delay NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
250 MHz
ns
ns
ns
ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
ps
ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f ≤ 150MHz
f ≤ 150MHz
ns
ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
ns
ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
ps
ps
tR, tF
Output Rise/Fall Time
odc Output Duty Cycle
0.5 to 1.8V
f < 134MHz
0.3 1.2 ns
45 50 55 %
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 1, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS83940I-01
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
www.DataSheet4U.com
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940I-01 is: 819
83940DYI-01
www.icst.com/products/hiperclocks.html
11
REV. A MARCH 1, 2004
11 Page | ||
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