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PDF ICS83940DI Data sheet ( Hoja de datos )
| Número de pieza | ICS83940DI | |
| Descripción | 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83940DI is a low skew, 1-to-18 LVPECL-
,&6 to-LVCMOS/LVTTL Fanout Buffer and a member
HiPerClockS™ of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83940DI has
two selectable clock inputs. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
www.DataSheedt4riUve.co5m0Ω series or parallel terminated transmission lines.
The ICS83940DI is characterized at 3.3V, 2.5V or mixed
3.3V core, 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83940DI ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
• 18 LVCMOS/LVTTL outputs
• Selectable LVCMOS_CLK or LVPECL clock inputs
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part to part skew: 750ps (maximum)
• 3.3V, 2.5V or mixed 3.3V core, 2.5V output supply modes
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC940L
BLOCK DIAGRAM
CLK_SEL
PCLK
nPCLK
LVCMOS_CLK
0
1
PIN ASSIGNMENT
18
Q0:Q17
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS83940DI 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q6
Q7
Q8
VDD
Q9
Q10
Q11
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
83940DYI
www.icst.com/products/hiperclocks.html
1
REV. A DECEMBER 12, 2002
1 page  
Integrated
Circuit
Systems, Inc.
ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions Minimum Typical
VIH
VIL
VPP
VCMR
Input High Voltage
LVCMOS_CLK
Input Low Voltage
LVCMOS_CLK
Peak-to-Peak Input Voltage PCLK, nPCLK
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK
2.4
300
VDD - 1.4
www.DataSheet4IIUN .com Input Current
VOH Output High Voltage
IOH = -20mA
1.8
VOL Output Low Voltage
IOL = 20mA
IDD Core Supply Current
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
Maximum
VDD
0.8
1000
VDD - 0.6
±200
0.5
25
Units
V
V
mV
V
µA
V
V
mA
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Output Frequency
PCLK, nPCLK;
tpLH
Propagation Delay
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
tpLH
Propagation Delay NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.7
1.7
1.6
1.8
250 MHz
3.2 ns
3.0 ns
3.4 ns
3.3 ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
150 ps
150 ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f ≤ 150MHz
f ≤ 150MHz
1.5 ns
1.3 ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
1.8 ns
1.5 ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
850 ps
750 ps
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
0.5 to 1.8V
0.5 to 1.8V
f < 134MHz
0.3 1.2 ns
0.3 1.2 ns
45 50 55 %
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI
www.icst.com/products/hiperclocks.html
5
REV. A DECEMBER 12, 2002
5 Page 
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
www.DataSheet4U.com
83940DYI
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
BBA
NOMINAL
MAXIMUM
N 32
A -- --
A1 0.05
--
A2 1.35 1.40
b 0.30 0.37
c 0.09 --
D 9.00 BASIC
D1 7.00 BASIC
D2 5.60 Ref.
E 9.00 BASIC
E1 7.00 BASIC
E2 5.60 Ref.
e 0.80 BASIC
L 0.45 0.60
q 0° --
ccc --
--
Reference Document: JEDEC Publication 95, MS-026
1.60
0.15
1.45
0.45
0.20
0.75
7°
0.10
www.icst.com/products/hiperclocks.html
11
REV. A DECEMBER 12, 2002
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS83940DI.PDF ] | |
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