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PDF ICS83908I-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS83908I-02 | |
| Descripción | 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
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PRELIMINARY
LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS
FANOUT BUFFER
ICS83908I-02
GENERAL DESCRIPTION
The ICS83908I-02 is a low skew, high performance
ICS 1-to-8 Crystal Oscillator/3.3V LVCMOS-to-3.3V
HiPerClockS™ LVCMOS fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS83908I-02 has selectable
single ended clock or two crystal-oscillator inputs. There is an
output enable to disable the outputs by placing them into a high-
impedance state.
www.DataSheet4U.com
Guaranteed output and part-to-part skew characteristics make
the ICS83908I-02 ideal for those applications demanding well
defined performance and repeatability.
FEATURES
• Eight LVCMOS/LVTTL outputs
(19Ω typical output impedance)
• Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
• Crystal input frequencry range: 10MHz - 40MHz
• Output frequency: 200MHz (typical) CLK0
• Output Skew: TBD
• Part to Part Skew: TBD
• RMS phase jitter @ 25MHz (100Hz - 1MHz):
0.22ps (typical) VDD = VDDO = 3.3V
Offset
Noise Power
100Hz ............. -111.4 dBc/Hz
1kHz ............. -139.9 dBc/Hz
10kHz ............. -157.3 dBc/Hz
100kHz ............. -157.5 dBc/Hz
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
BLOCK DIAGRAM
OE Pullup
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CLK_SEL0 Pulldown
CLK_SEL1 Pulldown
XTAL_IN0
XTAL_OUT0
OSC
00
PIN ASSIGNMENT
Q0
VDD
XTAL_IN0
XTAL_OUT0
VDDO
Q0
Q1
GND
Q2
Q3
VDDO
CLK_SEL0
CLK0
1
2
3
4
5
6
7
8
9
10
11
12
24 GND
23 XTAL_IN1
22 XTAL_OUT1
21 VDDO
20 Q7
19 Q6
18 GND
17 Q5
16 Q4
15 VDDO
14 CLK_SEL1
13 OE
XTAL_IN1
XTAL_OUT1
OSC
CLK0 Pulldown
01
10
11
8 LVCMOS Outputs
Q7
ICS83908I-02
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm
body package
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS FANOUT BUFFER
1 ICS83908AGI-02 REV. B JULY 24, 2007
1 page  
ICS83908I-02
LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER
PRELIMINARY
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C
Symbol
fMAX
tpLH
tsk(o)
Parameter
Output Frequency
w/External
XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Test Conditions
Minimum Typical Maximum Units
10 40 MHz
200 MHz
2 ns
TBD
ps
tsk(pp) Part-to-Part Skew; NOTE 2, 3
tjit(Ø)
RMS Phase Jitter, Random;
NOTE 2, 4
www.DataSthRe/ett4F U.comOutput Rise/Fall Time
odc Output Duty Cycle
25MHz, (100Hz - 1MHz)
20% to 80%
TBD
0.22
457
50
ps
ps
ps
%
tEN Output Enable Time; NOTE 5
tDIS Output Disable Time; NOTE 5
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
8
ns
ns
TABLE 6B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol
fMAX
tpLH
tsk(o)
Parameter
Output Frequency
w/External
XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Test Conditions
Minimum Typical Maximum Units
10 40 MHz
200 MHz
2.2 ns
TBD
ps
tsk(pp)
tjit(Ø)
tR / tF
odc
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
25MHz, (100Hz - 1MHz)
20% to 80%
TBD
0.21
463
50
ps
ps
ps
%
tEN Output Enable Time; NOTE 5
tDIS Output Disable Time; NOTE 5
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
10
8
ns
ns
IDT™ / ICS™ LVCMOS FANOUT BUFFER
5 ICS83908AGI-02 REV. B JULY 24, 2007
5 Page 
ICS83908I-02
LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER
APPLICATION INFORMATION
PRELIMINARY
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS83908I-02 has a built-in crystal oscillator
circuit. This interface can accept either a series or parallel
www.DatacSrhyesetta4Ul .wcoimthout additional components and generate fre-
quencies with accuracy suitable for most applications. Additional
accuracy can be achieved by adding two small capacitors C1
and C2 as shown in Figure 1. Typical results using parallel 18pF
crystals are shown in Table 5.
X1
18pF Parallel Crystal
XTAL_OUT
C1
15p
XTAL_IN
C2
15p
FIGURE 1. Crystal Input Interface
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
Ro Rs
.1uf
Zo = 50
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 2. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ LVCMOS FANOUT BUFFER
11 ICS83908AGI-02 REV. B JULY 24, 2007
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS83908I-02.PDF ] | |
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