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PDF ICS82C404 Data sheet ( Hoja de datos )
| Número de pieza | ICS82C404 | |
| Descripción | Dual Programmable Graphics Frequency Generator | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
ICS82C404
Advance Information
Dual Programmable Graphics Frequency Generator
General Description
The ICS82C404 is a fully programmable graphics clock gen-
erator. It can generate user specified clock frequencies using
an externally generated input reference or by a single crystal.
The output frequency is programmed by entering a 24-bit
www.DataSheedt4igUi.tcaolmword through the serial port.
Two fully user-programmable phase-locked loops are offered
in a single package. One PLL is designed to drive the memory
clock, while the second drives the video clock. The outputs
may be changed on-the-fly to any desired frequency between
390 kHz and 120 MHz. The ICS82C404 is ideally suited for
any design where multiple or varying frequencies are required.
This part is ideal for graphics applications. It generates low
jitter, high speed pixel clocks. It can be used to replace
multiple, expensive high speed crystal oscillators. The flexi-
bility of the device allows it to generate non-standard graph-
ics clocks.
The leader in the area of multiple clock output clocks on a
single chip, ICS has been shipping graphics frequency gener-
ators since October, 1990, and is constantly improving the
phase-locked loop. The ICS82C404 incorporates a patented
fourth generation PLL that offers the best jitter performance
available.
Features
• Pin-for-pin and function compatible with ICD’s version
of the 82C404
• Dual programmable graphics clock generator
• Memory and video clocks are individually programmable
“on-the-fly”
• Ideal for designs where multiple or varying frequencies
are required
• Increased frequency resolution from optional pre-divide-
by-2 on the M counter
• Output enable feature available for tristating outputs
• Independent clock outputs range from 390 kHz to
120 MHz
• Operation up to 140 MHz available
• Power-down capabilities
• Low-power, high speed 0.8µ CMOS technology
• Glitch-free transitions
• Available in 16-pin PDIP or SOIC package
Block Diagram
ICS82C404RevA111095
1 page  
ICS82C404
Serial Programming Architecture
The pins SEL0 and SEL1 perform the dual functions of select-
ing registers and serial programming. In serial programming
mode, SEL0 acts as a clock pin while SEL1 acts as the data pin.
The ICS82C404-01 may not be serially programmed when in
power-down mode.
Since the VCLK registers are selected by the SEL0 and SEL1
pins, and since any change in their state may affect the output
frequency, new data input on the selection bits is only permitted
to pass through the decode logic after the watchdog timer has
timed out. This delay of SEL0 or SEL1 data permits a serial
program cycle to occur without affecting the current register
selection.
In order to program a particular register, an unlocking sequence
must occur. The unlocking sequence is detailed in the following
www.DataSheetit4mUi.ncgomdiagram:
Serial Data Register
The serial data is clocked into the serial data register in the
order described in Figure 1 below (Serial Data Timing).
The serial data is sent as follows: An individual data bit is
sampled on the rising edge of CLK. The complement of the
data bit must be sampled on the previous falling edge of CLK.
The set-up and hold time requirements must be met on both
CLK edges. For specifics on timing, see the timing diagrams
on pages 10, 11 and 12.
The unlock sequence consists of at least five low-to-high
transitions of CLK while data is high, followed immediately
by a single low-to-high transition while data is low. Following
this unlock sequence, data can be loaded into the serial data
register.
Following any transition of CLK or DATA, the watchdog timer
is reset and begins counting. The watchdog timer ensures that
successive rising edges of CLK and DATA do not violate the
time-out specification of 2ms. If a time-out occurs, the lock
mechanism is reset and the data in the serial data register is
ignored.
The bits are shifted in this order: a start bit, 21 data bits, 3
address bits (which designate the desired register), and a stop
bit. A total of 24 bits must always be loaded into the serial data
register or an error is issued. Following the entry of the last
data bit, a stop bit or load command is issued by bringing DATA
high and toggling CLK high-to-low and low-to-high. The
unlocking mechanism then resets itself following the load.
Only after a time-out period are the SEL0 and SEL1 pins
allowed to return to a register selection function.
Figure 1: Serial Data Timing
5
5 Page 
www.DataSheet4U.com
ICS82C404
Selection Timing
MCLK and Active VCLK Register Programming Timing
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS82C404.PDF ] | |
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