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PDF ADS7823 Data sheet ( Hoja de datos )
| Número de pieza | ADS7823 | |
| Descripción | Sampling A/D Converter | |
| Fabricantes | Burr-Brown Corporation | |
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ADS7823
SBAS180B – JUNE 2001 - REVISED SEPTEMBER 2003
12-Bit, Sampling A/D Converter
with I2C™ INTERFACE
FEATURES
www.DataSheet4U.cqom50kHz SAMPLING RATE
q NO MISSING CODES
q 2.7V TO 5V OPERATION
q FOUR-WORD FILO
q A0, A1 ADDRESS PINS
q I2C INTERFACE SUPPORTS:
Standard, Fast, and High-Speed Modes
q MSOP-8 PACKAGE
APPLICATIONS
q VOLTAGE SUPPLY MONITORING
q ISOLATED DATA ACQUISITION
q TRANSDUCER INTERFACE
q BATTERY-OPERATED SYSTEMS
q REMOTE DATA ACQUISITION
DESCRIPTION
The ADS7823 is a single-supply, low-power, 12-bit data
acquisition device that features a serial I2C interface. The
Analog-to-Digital (A/D) converter features a sample-and-
hold amplifier and internal, asynchronous clock. The combi-
nation of an I2C serial two-wire interface and micropower
consumption makes the ADS7823 ideal for applications
requiring the A/D converter to be close to the input source in
remote locations and for applications requiring isolation. The
ADS7823 is available in an MSOP-8 package.
VREF
AIN
S/H Amp
SAR
CDAC
Comparator
Serial
Interface
SDA
SCL
A0
A1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2001-2003, Texas Instruments Incorporated
1 page  
TIMING CHARACTERISTICS(1)
At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
www.DataSheet4U.com
Setup Time for a Repeated START
Condition
Data Setup Time
Data Hold Time
Rise Time of SCL Signal
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP Condition
Capacitive Load for SDA and SCL
Line
Pulse Width of Spike Suppressed
Noise Margin at the HIGH Level for
Each Connected Device (Including
Hysteresis)
SYMBOL
fSCL
tBUF
tHD;STA
tLOW
tHIGH
tSU;STA
tSU;DAT
tHD;DAT
tRCL
tRCL1
tFCL
tRDA
tFDA
tSU;STO
CB
tSP
VNH
CONDITIONS
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max
High-Speed Mode, CB = 400pF max
Standard Mode
Fast Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode, CB = 100pF max(2)
High-Speed Mode, CB = 400pF max(2)
Standard Mode
Fast Mode
High-Speed Mode
Fast Mode
High-Speed Mode
Standard Mode
Fast Mode
High-Speed Mode
MIN
4.7
1.3
4.0
600
160
4.7
1.3
160
320
4.0
600
60
120
4.7
600
160
250
100
10
0
0
0(3)
0(3)
20 + 0.1CB
10
20
20 + 0.1CB
10
20
20 + 0.1CB
10
20
20 + 0.1CB
10
20
20 + 0.1CB
10
20
4.0
600
160
0.2VDD
MAX
100
400
3.4
1.7
3.45
0.9
70
150
1000
300
40
80
1000
300
80
160
300
300
40
80
1000
300
80
160
300
300
80
160
400
50
10
UNITS
kHz
kHz
MHz
MHz
µs
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
pF
ns
ns
V
Noise Margin at the LOW Level for
Each Connected Device (Including
Hysteresis)
VNL
Standard Mode
Fast Mode
High-Speed Mode
0.1VDD
V
NOTES: (1) All values referred to VIHMIN and VILMAX levels. (2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with
a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
ADS7823
SBAS180B
5
5 Page 
READING DATA
Data can be read from the ADS7823 by read-addressing the
part (LSB of address byte set to 1) and receiving the
transmitted bytes. Converted data can only be read from the
ADS7823 once a conversion has been initiated as described
in the preceding section.
Each 12-bit data word is returned in two bytes, as shown
below, where D11 is the MSB of the data word, and D0 is the
LSB. Byte 0 is sent first, followed by Byte 1.
BYTE0
BYTE1
MSB
0
D7
6
0
D6
5 4 3 2 1 LSB
0 0 D11 D10 D9 D8
D5 D4 D3 D2 D1 D0
READING IN F/S MODE
www.DataSheet4U.cInomFast and Standard (F/S) modes, the A/D converter has
time to make four complete conversions between the recep-
tion of bit 5 of the command byte and the complete reception
of the read address, even when operating in Fast mode.
Because the ADS7823 can perform these conversions much
faster than they can be transmitted in F/S mode, data is
stored in a four-level FILO. During the read operation, the A/
D converter is powered down and the contents of the stack
are read out one by one in the correct order.
A typical transfer sequence for reading four words of data in
F/S mode (see Figure 3). Note that the master sends a not-
acknowledge after the fourth data word has been read. This
tells the ADS7823 that no further reads will be performed. No
more than four data words should be read at a time; further
reads will return undefined data.
Although a STOP condition is shown at the end of the figure,
it is permissible to issue a repeated START; this will have the
same effect.
READING IN HS MODE
High Speed (HS) mode is fast enough that codes can be
read out one at a time, without employing the FILO. In HS
mode there is not enough time for a single conversion to
complete between the reception of command bit 5 and the
read address byte, so the ADS7823 stretches the clock after
the command byte has been fully received, holding it LOW
until the conversion is complete.
A typical read sequence for HS mode is shown in Figure 4.
Included in the read sequence is the shift from
F/S to HS modes. It may be desirable to remain in HS mode
after reading a code; to do this, issue a repeated START
instead of a STOP at the end of the read sequence, since a
STOP causes the part to return to F/S mode.
It is very important not to read more than one code at a time
from the ADS7823 during HS mode. If codes are read out
more than one at a time, as in F/S mode, the results for all
codes (except the first) are undefined, and the data stream
will be corrupt.
F/S Mode
S0 0 0 0 1 XXXN
HS Mode Master Code
HS Mode Enabled
ADC Power-Down Mode
ADC Wake-Up Mode
Sr 1 0 0 1 0 A1 A0 W A 0 0 0 X X X X X A SCLH is stretched in wait-state
Write-Addressing Byte
Command Byte
HS Mode Enabled
ADC Power-Down Mode
Return to
F/S Mode
See Note B
Sr 1 0 0 1 0 A1 A0 R A 0 0 0 0 D11 D10 D9 D8 A D7 D6 . . .D1 D0 N P
Read-Addressing Byte
(see Note A)
2×(8 bits + ack/not-ack)
From master to slave
From slave to master
A = acknowledge (SDA Low)
N = not-acknowledge (SDA High)
S = START Condition
P = STOP Condition
Sr = repeated START Condition
W = 0 (WRITE)
R = 1 (READ)
NOTES: (A) Failure for master to send read-addressing byte—setting R/W flag to “1”—will result in internal clock remaining ON, increasing power consumption.
(B) Use repeated START to remain in HS mode instead of STOP.
FIGURE 4. Typical Read Sequence in HS Mode.
ADS7823
SBAS180B
11
11 Page | ||
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| PDF Descargar | [ Datasheet ADS7823.PDF ] | |
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