PDF TB1311AFG Data sheet ( Hoja de datos )

Número de pieza	TB1311AFG
Descripción	Sync Separation and H/V Frequency Counter IC
Fabricantes	Toshiba Semiconductor
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No Preview Available ! TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB1311AFG TB1311AFG Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs The TB1311AFG includes audio and video SW blocks, prefilters for A/D converters, sync separators, and an H/V format detector for TV signals. The TB1311AFG contributes to a reduction in the proportion of the PCB occupied by LCR filters and to the simplification of designs on www.DataSheet4U.comanalog interfaces. The TB1311AFG has an I2CBUS interface through which various functions can be controlled. P-QFP80-1420-0.80C Weight: 1.6 g (typ.) Features Audio SW block ・ Audio (L/R) inputs ・ Audio (L/R) output: 3 channels Audio block ・ Attenuator Video SW block ・ CVBS inputs ・ Y/C inputs ・ Component video inputs (co-use as RGB inputs) ・ SCART inputs ・ Output: 2 channels ・ Monitor output Video block ・ Gain switching: -3 dB / 0 dB / +3 dB ・ Bandwidth filter: prefilter for ADC; 4.5 to 46 MHz variable Sync separation block ・ Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i, VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60 ・ HD/VD input: 1 channel; positive and negative input acceptable ・ HD/VD output: positive and negative output selectable ・ Masking pseudo-sync for the copyguard signal Others ・ Line detector for Japanese D-pin ・ S2, S1, insertion detection for S-pin ・ Horizontal and vertical frequency counter ・ Format detection circuit to input signal ・ No-input detection ・ Automatic sync process switching mode ・ Programmable number of audio/video inputs 1 2006-05-29 1 page Block Diagram 4 (Other Blocks) www.DataSheet4U.com TB1311AFG This IC does not support weak signals, ghost signals or other nonstandard signals. Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes. 5 2006-05-29 5 Page TB1311AFG BUS Control Map Write Mode Slave Address: DEH www.DataSheet4U.com SA D7 D6 D5 D4 D3 D2 D1 D0 PRESET 00 CVBS1OUT fc HALF1 YCbCr1OUT 00000000 01 CVBS2OUT fc HALF2 YCbCr2OUT 00000000 02 (0) FILPASS2 FILPASS1 YC MIX MON OUT 00000000 03 f0 SW1 BANDWIDTH1 00000000 04 f0 SW2 BANDWIDTH2 00000000 05 CVBS2 GAIN YCbCr2 GAIN CVBS1 GAIN YCbCr1 GAIN 00000000 06 CbCr PIN4 CbCr PIN3 CbCr PIN2 CbCr PIN1 CLAMP4 CLAMP3 CLAMP2 CLAMP1 00000000 07 FB2 DL FB2 MUTE FB2 OUT FB1 DL FB1 MUTE FB1 OUT 00000000 08 AU2 OUT AU1 OUT 00010001 09 AU1 FIX AU1 ATT 00000000 0A AU2 FIX AU2 ATT 00000000 0B AU10 PIN AU9 PIN AU8 PIN (0) AU3 OUT 00000001 0C HV-SEP2 HV-SEP1 (0) (0) SYNC LPF2 SYNC LPF1 00000000 0D A-SYNC SIG LPF (0) (0) Yvi OUT 00000000 0E (0) PS MASK V-DET HD WIDTH HV POL (0) HV DET HV OUT 00000000 0F H DMY V DMY FB2 PIN-M HV FREQ2 00000000 10 H COUNT MAX (0) H COUNT MIN 00000000 11 SIG DET N SIG RESET N 00000000 12 (0)TEST1 FB2 PIN-L SIG RESET SIG SW SIG DET IMPE SIG DET LVL 00000000 13 (00000000) TEST2 00000000 14 (00000000) TEST3 00000000 Remark: SA = Sub-address. NOTE: Set 0 (zero) on bits written as (0). Read Mode Slave Address: DFH D7 D6 D5 D4 D3 D2 D1 D0 0 POR H FM2 V FM2 1 H FORMAT 2 FB DET2 FB DET1 SIG DET H IN V IN V-SYNC-W HD-POL V FORMAT HV-OUT FORMAT VD-POL ∗ 3 DC4 DC3 DC2 DC1 4 DC8 DC7 DC6 DC5 5 DC12 DC11 DC10 DC9 6 S8 S7 S6 S5 S4 S3 S2 S1 7 H FREQ DET 8 V FREQ DET ∗: Undefined 11 2006-05-29 11 Page

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Número de pieza	Descripción	Fabricantes
TB1311AFG	Sync Separation and H/V Frequency Counter IC	Toshiba Semiconductor

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