PDF MAX3886 Data sheet ( Hoja de datos )

Número de pieza	MAX3886
Descripción	Multirate CDR
Fabricantes	Maxim Integrated Products
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No Preview Available ! 19-3103; Rev 0; 12/07 Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications General Description The MAX3886 2.488Gbps/1.244Gbps/622Mbps CDR with SerDes (serializer/deserializer) is designed specifi- cally for low-cost optical network terminal (ONT) appli- cations in Gigabit passive optical network (GPON) and broadband passive optical network (BPON) fiber-to- the-home (FTTH) systems. It provides G.984- and G.983-compliant clock and data recovery (CDR) for the www.DataSheect4oUn.ctionmuous downstream data signal, with an integrated 4-bit SerDes that has LVDS parallel interfaces and CML serial interfaces. The SerDes uses the recovered downstream clock for upstream serialization (loopback clock), providing opti- mum PON operation. The CDR frequency reference can be provided by a low-cost 19.44MHz SMD-type crystal or external LVCMOS source, and excellent jitter tolerance supports applications requiring FEC. An inte- grated burst-enable signal path also simplifies high- performance upstream burst timing. This 3.3V IC is housed in a 8mm x 8mm, 56-lead thin QFN package and operates from -40°C to +85°C. Applications BPON/GPON Optical Network Terminal (ONT) Features ♦ 2.488Gbps, 1.244Gbps, and 622Mbps Clock and Data Recovery ♦ Meets G.984 and G.983 Jitter Requirements ♦ 4-Bit Serializer and 4-Bit Deserializer with Loop-Timed Serialization ♦ CML Serial I/O, LVDS Parallel I/O ♦ Integrated Reference Oscillator Uses 19.44MHz SMD Crystal ♦ Integrated Upstream Burst-Enable Signal Path Ordering Information PART TEMP RANGE PIN- PACKAGE PKG CODE MAX3886ETN+ -40°C to +85°C +Denotes a lead-free package. 56 TQFN (8mm x 8mm) T5688-2 Pin Configuration appears at end of data sheet. Typical Application Circuit +3.3V +3.3V 0.27μF 19.4400MHz VCC CFIL VCC +3.3V RFCK1 MVCO MDDR MSYM 1490nm MAX3747/ 2.488G MAX3748 LIM AMP RFCK2 SDI MAX3886 GPON CDR/SERDES PCKO PDO[3:0] PON BiDi TRIPLEXER 1310nm MAX3643/ MAX3656 LD DRIVER 1.244G SDO BENO PDI[3:0] PCKI BENI GND LOCK FRST FERR MAC IC PCLK (311MHz) PDATA (622Mbps) PDATA (311Mbps) PCLK (311MHz) BURST ENABLE VOICE SLIC DATA 10/100 ETHERNET 1550nm MAX3654 VIDEO TIA GPON OPTICAL NETWORK TERMINAL (ONT) 870MHz VIDEO ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 page Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications PDO_ PCKO www.DataSheet4(UM.DcDoRm= 0) PCKO (MDDR = 1) 1UI tCK-Q MIN tCK-Q MAX 1UI PDI_ PCKI tSU tHD Figure 1. Parallel Interface Timing Diagrams SDO PDI1 PDI0 PDI3 PDI2 PDI1 BENO tB-MSB MIN tB-MSB MAX Figure 2. Burst-Enable Timing LVDS VOUT- SINGLE- ENDED OUTPUT VOUT+ DIFFERENTIAL OUTPUT RL = 100Ω VOD Figure 3. Definition of LVDS Output Levels V VOD VOS +VOD 0V -VOD VOD(P-P) = VOUT+ - VOUT- _______________________________________________________________________________________ 5 5 Page Multirate CDR with Integrated Serializer/Deserializer for GPON and BPON ONT Applications Burst-Enable Signal Processing To minimize PON overhead, it is important that the laser driver burst-enable (BEN) signal correspond accurately with the beginning of the serial data burst. This is sup- ported in the MAX3886 by the BENI LVDS input and associated signal path. The LVDS burst-enable signal from the MAC layer IC is passed through the same FIFO as the parallel data and output on the BENO CML out- www.DataSheetp4uUt.,cowmhich ensures that the laser driver’s burst enable matches the beginning of the associated serial MSB. If FRST or FERR are high, the BENO output is forced low to prevent the laser driver from transmitting erroneous data. The parallel data setup and hold timing require- ments also apply to the burst-enable signal. Lock Detector Output The lock detector operates by comparing a divided- down version of the VCO output to the reference clock. The LOCK output pin indicates lock (high) when the fre- quency difference between the reference clock and the CDR VCO is less than 250ppm, within the “pullin” range of the PLL. The LOCK output indicates out-of-lock (low) when the frequency difference between the reference clock and the CDR VCO becomes more than 500ppm. When valid input data is present, this provides a stable lock indication. At power-up, the CDR takes approximately 50ms (if valid NRZ data is present) for initial acquisition while the internal reference oscillator, the PLL, and the fre- quency detector reach their operating conditions. During this startup period, the LOCK status output may provide false indication of a lock condition. Once the PLL and frequency detector are initialized, the nominal time for reacquisition of an NRZ input is 2ms. When valid NRZ input data is not present, the lock detector may produce a chattering LOCK indicator out- put while the PLL searches for the input frequency. If needed, an external digital filter can be used to mask this chattering. Table 1. Lock Detector Output CDR INPUT Valid NRZ data No CDR input LOCK OUTPUT 1 0/1 (chatter) Control Input Summary Table 2 summarizes the clock and data rates as con- trolled by MVCO, MSYM, and MDDR. Table 2. Clock and Data Rate Controls MVCO 0 0 0 0 Open Open Open Open 1 1 1 1 MSYM 0 0 1 1 0 0 1 1 0 0 1 1 MDDR 0 1 0 1 0 1 0 1 0 1 0 1 Rx SDI RATE PDO RATE (Mbps) (Mbps) 622 622 622 622 1244 1244 1244 1244 2488 2488 2488 2488 155 155 155 155 311 311 311 311 622 622 622 622 PCKO (MHz) 155 78 155 78 311 155 311 155 622 311 622 311 Tx SDO RATE PDI RATE (Mbps) (Mbps) PCKI (MHz) 155 155 622 622 622 622 1244 1244 1244 1244 2488 2488 39 39 155 155 155 155 311 311 311 311 622 622 39 39 155 155 155 155 311 311 311 311 622 622 RCKO (MHz) 39 39 155 155 155 155 311 311 311 311 622 622 ______________________________________________________________________________________ 11 11 Page

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