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PDF MAX3881 Data sheet ( Hoja de datos )
| Número de pieza | MAX3881 | |
| Descripción | SDH/SONET 1:16 Deserializer | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MAX3881 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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19-1996; Rev 1; 12/01
EVAALVUAAILTAIOBNLEKIT
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
The MAX3881 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers sin-
gle-ended PECL parallel data outputs and a differential
PECL parallel clock output for interfacing with digital
www.DataSheecti4rcUu.ciotrmy.
The MAX3881 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3881’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3881 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP package.
Features
o Single +3.3V Supply
o 530mW Operating Power
o Fully Integrated Clock Recovery and Data
Retiming
o Exceeds ANSI, ITU, and Bellcore Specifications
o Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o 2.488Gbps Serial to 155Mbps Parallel Conversion
o Differential PECL Clock Output
o Single-Ended PECL Data Outputs
o Tolerates >2000 Consecutive Identical Digits
o Loss-of-Lock Indicator
PART
MAX3881ECB
*Exposed pad
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP-EP*
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
Typical Application Circuit appears at end of data sheet.
TOP VIEW
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
FIL+
FIL-
VCC
PHADJ+
PHADJ-
VCC
SDI+
SDI-
VCC
SLBI+
SLBI-
VCC
SIS
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MAX3881
48 VCC
47 PD10
46 VCC
45 PD9
44 VCC
43 PD8
42 VCC
41 GND
40 VCC
39 PD7
38 VCC
37 PD6
36 VCC
35 PD5
34 VCC
33 GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
*EXPOSED PAD IS CONNECTED TO GND.
TQFP-EP*
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
1, 15, 16, 17,
25, 33, 41,
49, 57, 62,
64
www.DataSheet4U.com2
3
4, 7, 10, 13,
20, 22, 24,
26, 28, 30,
32, 34, 36,
38, 40, 42,
44, 46, 48,
50, 52, 54,
56, 58, 60
5
NAME
GND
FIL+
FIL-
VCC
PHADJ+
6 PHADJ-
8 SDI+
9 SDI-
11 SLBI+
12 SLBI-
14 SIS
18
19
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
PCLK+
PCLK-
PD0 to PD15
63 LOL
EP Exposed Pad
FUNCTION
Ground
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
+3.3V Supply Voltage
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Positive Parallel Clock PECL Output
Negative Parallel Clock PECL Output
Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 2).
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pullup resistor).
The LOL monitor is valid only when a data stream is present on the inputs to the MAX3881.
Ground. This must be soldered to a circuit board for proper electrical and thermal performance
(see Package Information).
_______________________________________________________________________________________ 5
5 Page 
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Package Information (continued)
www.DataSheet4U.com
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MAX3881.PDF ] | |
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