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PDF EDS6432CFTA Data sheet ( Hoja de datos )
| Número de pieza | EDS6432CFTA | |
| Descripción | 64M bits SDRAM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
64M bits SDRAM
EDS6432AFTA, EDS6432CFTA
(2M words × 32 bits)
Description
The EDS6432AFTA, EDS6432CFTA are 64M bits
SDRAMs organized as 524,288 words × 32 bits × 4
banks. All inputs and outputs are synchronized with
www.DataSheet4Ut.hcoempositive edge of the clock.
Supply voltages are 3.3V (EDS6432AFTA) and 2.5V
(EDS6432CFTA).
It is packaged in 86-pin plastic TSOP (II).
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
86-pin Plastic TSOP(II)
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 12
DQ7 13
NC 14
VDD 15
DQM0 16
/WE 17
/CAS 18
/RAS 19
/CS 20
NC 21
BA0 22
BA1 23
A10(AP) 24
A0 25
A1 26
A2 27
DQM2 28
VDD 29
NC 30
DQ16 31
VSSQ 32
DQ17 33
DQ18 34
VDDQ 35
DQ19 36
DQ20 37
VSSQ 38
DQ21 39
DQ22 40
VDDQ 41
DQ23 42
VDD 43
86 VSS
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VDDQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VDDQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 NC
56 DQ31
55 VDDQ
54 DQ30
53 DQ29
52 VSSQ
51 DQ28
50 DQ27
49 VDDQ
48 DQ26
47 DQ25
46 VSSQ
45 DQ24
44 VSS
(Top view)
A0 to A10 Address input
BA0, BA1 Bank select address
DQ0 to DQ31 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM0 to DQM3 Input output mask
CKE
Clock enable
CLK Clock input
VDD
Power for internal circuit
VSS
Ground for internal circuit
VDDQ
Power for DQ circuit
VSSQ
Ground for DQ circuit
NC No connection
Document No. E0487E50 (Ver. 5.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
1 page  
EDS6432AFTA, EDS6432CFTA
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6432AF]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6432CF]
EDS6432AF EDS6432CF
Parameter
Symbol
Grade max.
max.
Unit Test condition
Notes
Operating current
IDD1
-6B 120
-75 100
120
100
mA
Burst length = 1
tRC = tRC (min.)
1, 2, 3
Standby current in power
down
IDD2P
3
3
mA
CKE = VIL,
tCK = tCK (min.)
6
Standby current in power
down (input signal stable)
IDD2PS
2 2 mA CKE = VIL, tCK = ∞ 7
Standby current in non power
down
IDD2N
20
20
mA
CKE, /CS = VIH,
tCK = tCK (min.)
4
Standby current in non power
down (input signal stable)
IDD2NS
9
9
mA
CKE = VIH, tCK = ∞,
/CS = VIH
8
Active standby current in
www.DataSheet4Up.coowmer down
IDD3P
4
4
mA
CKE = VIL,
tCK = tCK (min.)
1, 2, 6
Active standby current in
power down (input signal
stable)
IDD3PS
3 3 mA CKE = VIL, tCK = ∞ 2, 7
Active standby current in non
power down
IDD3N
40
40
mA
CKE, /CS = VIH,
tCK = tCK (min.)
1, 2, 4
Active standby current in non
power down (input signal
IDD3NS
stable)
30
30
mA
CKE = VIH, tCK = ∞,
/CS = VIH
2, 8
Burst operating current
IDD4
-6B 150
-75 130
150
130
mA
tCK = tCK (min.),
BL = 4
1, 2, 5
Refresh current
IDD5
-6B 260
-75 220
260
220
mA tRC = tRC (min.)
3
Self refresh current
IDD6
1.5
1.5
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0487E50 (Ver. 5.0)
5
5 Page 
EDS6432AFTA, EDS6432CFTA
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
www.DataSheet4U.com
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A10 (input pins)
Row Address is determined by A0 to A10 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
L
Bank 1
H
Bank 2
L
Bank 3
H
Remark: H: VIH. L: VIL.
BA1
L
L
H
H
DQM (input pins)
DQM controls I/O buffers. DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to
DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is
high. The DQM latency for the write is zero.
DQ0 to DQ31 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0487E50 (Ver. 5.0)
11
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