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PDF EDS6416CHBH Data sheet ( Hoja de datos )
| Número de pieza | EDS6416CHBH | |
| Descripción | 64M bits SDRAM | |
| Fabricantes | Elpida Memory | |
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DATA SHEET
64M bits SDRAM
EDS6416AHBH, EDS6416CHBH
(4M words × 16 bits)
Description
The EDS6416AHBH, EDS6416CHBH are 64M bits
SDRAMs organized as 1,048,576 words × 16 bits × 4
banks. All inputs and outputs are synchronized with
www.DataSheet4Ut.hcoempositive edge of the clock.
Supply voltages are 3.3V (EDS6416AHBH) and 2.5V
(EDS6416CHBH).
It is packaged in 60-ball FBGA.
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8, full page)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• FBGA package with lead free solder (Sn-Ag-Cu)
RoHS compliant
Pin Configurations
/xxx indicate active low signal.
60-ball FBGA
1234567
A
VSS DQ15
B
DQ14 VSSQ
C
DQ13 VDDQ
D
DQ12 DQ11
DQ0 VDD
VDDQ DQ1
VSSQ DQ2
DQ4 DQ3
E
DQ10 VSSQ
VDDQ DQ5
F
DQ9 VDDQ
G
DQ8 NC
VSSQ DQ6
NC DQ7
H
NC VSS
J
NC UDQM
VDD NC
LDQM /WE
K
NC CLK
L
CKE NC
M
A11 A9
N
A8 A7
P
A6 A5
R
VSS A4
/RAS /CAS
NC /CS
BA1 BA0
A0 A10
A2 A1
A3 VDD
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0442E40 (Ver. 4.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2004-2005
1 page  
EDS6416AHBH, EDS6416CHBH
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V) [EDS6416AH]
(TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) [EDS6416CH]
EDS6416AH EDS6416CH
Parameter
Symbol
Grade max.
max.
Unit Test condition
Notes
Operating current
IDD1
-6B 120
-75 100
—
100
mA
Burst length = 1
tRC = tRC (min.)
1, 2, 3
Standby current in power
down
IDD2P
3
3
mA
CKE = VIL,
tCK = tCK (min.)
6
Standby current in power
down (input signal stable)
IDD2PS
2 2 mA CKE = VIL, tCK = ∞ 7
Standby current in non power
down
IDD2N
20
20
mA
CKE, /CS = VIH,
tCK = tCK (min.)
4
Standby current in non power
down (input signal stable)
IDD2NS
9
9
mA
CKE = VIH, tCK = ∞,
/CS = VIH
8
Active standby current in
www.DataSheet4Up.coowmer down
IDD3P
4
4
mA
CKE = VIL,
tCK = tCK (min.)
1, 2, 6
Active standby current in
power down (input signal
stable)
IDD3PS
3 3 mA CKE = VIL, tCK = ∞ 2, 7
Active standby current in non
power down
IDD3N
35
35
mA
CKE, /CS = VIH,
tCK = tCK (min.)
1, 2, 4
Active standby current in non
power down (input signal
IDD3NS
stable)
20
20
mA
CKE = VIH, tCK = ∞,
/CS = VIH
2, 8
Burst operating current
IDD4
-6B 140
-75 120
—
120
mA
tCK = tCK (min.),
BL = 4
1, 2, 5
Refresh current
IDD5
-6B 260
-75 220
—
220
mA tRC = tRC (min.)
3
Self refresh current
IDD6
1.5
1.5
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. IDD depends on output load condition when the device is selected. IDD (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Data Sheet E0442E40 (Ver. 4.0)
5
5 Page 
EDS6416AHBH, EDS6416CHBH
Pin Function
CLK (input pin)
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE (input pins)
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is
invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends
operation.
When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode.
During power down mode, CKE must remain low.
/CS (input pins)
/CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue.
www.DataSheet4U.com
/RAS, /CAS, and /WE (input pins)
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the
command table.
A0 to A11 (input pins)
Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle.
Column Address is determined by A0 to A7 at the CLK rising edge in the read or write command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged;
when A10 is low, only the bank selected by BA0 and BA1 is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically after the burst access.
BA0 and BA1 (input pin)
BA0 and BA1 are bank select signal (BS). (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
Bank 0
L
Bank 1
H
Bank 2
L
Bank 3
H
Remark: H: VIH. L: VIL.
BA1
L
L
H
H
UDQM and LDQM (input pins)
UDQM and LDQM control input/output buffers. UDQM and LDQM control upper byte (DQ8 to DQ15) and lower byte
(DQ0 to DQ7).
DQ0 to DQ15 (input/output pins)
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0442E40 (Ver. 4.0)
11
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