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PDF AD5626 Data sheet ( Hoja de datos )
| Número de pieza | AD5626 | |
| Descripción | 12-Bit nanoDAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
8-lead MSOP and 8-lead LFCSP packages
Complete voltage output with internal reference
1 mV/bit with 4.095 V full scale
5 V single-supply operation
No external components required
3-wire serial interface, 20 MHz data loading rate
www.DataSheeLt4oUw.cpoomwer: 2.5 mW
APPLICATIONS
Portable instrumentation
Digitally controlled calibration
Servo controls
Process control equipment
PC peripherals
5 V, 12-Bit nanoDAC, Serial Interface
in MSOP and LFCSP Packages
AD5626
GENERAL DESCRIPTION
The AD5626, a member of the nanoDAC® family, is a complete
serial input, 12-bit, voltage output digital-to-analog converter
(DAC) designed to operate from a single 5 V supply. It contains
the DAC, input shift register and latches, reference, and a rail-
to-rail output amplifier. The AD5626 monolithic DAC offers
the user low cost and ease of use in 5 V only systems.
Coding for the AD5626 is natural binary with the MSB loaded
first. The output op amp can swing to either rail and is set to a
range of 0 V to 4.095 V for a one-millivolt-per-bit resolution. It
is capable of sinking and sourcing 5 mA. An on-chip reference
is laser trimmed to provide an accurate full-scale output voltage
of 4.095 V.
This part features a serial interface that is high speed, three-
wire, DSP compatible with data in (SDIN), clock (SCLK), and
load strobe (LDAC). There is also a chip-select pin for
connecting multiple DACs.
The CLR input sets the output to zero scale at power on or upon
user demand.
The AD5626 is specified over the extended industrial tempera-
ture range (–40°C to +85°C). The AD5626 is available in MSOP
and LFCSP surface-mount packages.
FUNCTIONAL BLOCK DIAGRAM
VDD
AD5626
REF
LDAC
CLR
DAC REGISTER
12-BIT DAC
OUTPUT
BUFFER
VOUT
INPUT
REGISTER
CS SCLK SDIN
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
Logic Inputs to GND
VOUT to GND
IOUT Short Circuit to GND
Package Power Dissipation
Thermal Resistance (θJA)
8-Lead MSOP
8-Lead LFCSP
www.DataSheeMt4aUx.icmoumm Junction Temperature
(TJ max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
Soldering
Rating
−0.3 V to +10 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
50 mA
(TJ max − TA)/θJA
220°C/W
62°C/W
150°C
−40°C to +85°C
−65°C to +150°C
JEDEC industry standard
J-STD-020
AD5626
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 20
5 Page 
voltage vs. load current plot, shown in Figure 11, provides
information for operation below VDD = 4.75 V.
TIMING AND CONTROL
The AD5626 has a separate serial input register from the
12-bit DAC register that allows preloading of a new data value
into the serial register without disturbing the present DAC
output voltage. After the new value is fully loaded in the serial
input register, it can be asynchronously transferred to the DAC
AD5626
register by strobing the LDAC pin. The DAC register uses a
level sensitive LDAC strobe that should be returned high before
any new data is loaded into the serial input register. At any time,
the contents of the DAC register can be reset to zero by strobing
the CLR pin that causes the DAC output voltage to go to zero
volts. Figure 2 details all of the timing requirements together
with Table 5, the control logic truth table.
www.DataSheet4U.com
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5626.PDF ] | |
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