|
|
PDF LHF32J02 Data sheet ( Hoja de datos )
| Número de pieza | LHF32J02 | |
| Descripción | Flash Memory 32M (2M bb 16/4M bb 8) | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LHF32J02 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F320BJE-PTTL90
Flash Memory
32M (2M × 16/4M × 8)
(Model No.: LHF32J02)
Spec No.: EL124011
Issue Date: April 17, 2000
1 page  
SHAR!=
LJSF32JO2
--
1 INTRODUCTION
This datasheet contains LH28F320BJE-PI-l-L90
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4 and 5 describe the memory
organization and functionality. Section 6 covers electrical
specifications.
1.1 Features
Key enhancements of LH28F320BJE-PTTL90 boot block
Flash memory are:
*Single low voltage operation
*Low power consumption
*Enhanced Suspend Capabilities
*Boot Block Architecture
Please note following:
l VCCvtK has been lowered to l.OV to support 2.7V-
3.6V block erase, full chip erase, word/byte write and
lock-bit configuration operations. The V,, voltage
transitions to GND is recommended for designs that
switch V,,, off during read operation.
1.2 Product Overview
The LH28F320BJE-PTTL90 is a high-performance 32M-
Iit Boot Block Flash memory organized as 2M-word of 16
)its or 4M-byte of 8 bits. The 2M-word/4M-byte of data is
u-ranged in two 4K-word/8K-byte boot blocks, six 4K-
vord/8K-byte parameter blocks and sixty-three 32K-
vord/64K-byte main blocks which are individually
:rasable, lockable and unlockable in-system. The memory
nap is shown in Figure 3.
The dedicated Vccw pin gives complete data protection
vhen Vccw<V,m,.
, Command User Interface (CUI) serves as the interface
etween the system processor and internal operation of the
evice. A valid command sequence written to the CUI
vitiates device automation. An internal Write State
lachine (WSM) automatically executes the algorithms
Id timings necessary for block erase. full chip erase.
,ord/byte write and lock-bit configuration operations.
A block erase operation erases one of the device’s 32K
word/64K-byte blocks typically within 1.2s (3V V,,. 3\
Vccw), 4K-word/8K-byte blocks typically within 0.6s (3\
V,,. 3V Vccw) independent of other blocks. Each block
can be independently erased minimum 100.000 times
Block erase suspend mode allows system software tc
suspend block erase to read or write data from any other
block.
Writing memory data is performed in word/byu
increments of the device’s 32K-word blocks typically
within 33~s (3V V,,. 3V V,,,), 6JK-byte block!
typically within 31ps (3V V,,. 3V Vccw). 4K-wore
blocks typically within 36~s (3V V,,. 3V Vccw). 8K-
byte blocks typically within 32~s (3V V,,. 3V Vccw).
‘IWord/byte write suspend mode enables the system to reac
data or execute code from any other flash memory array
location.
Individual block locking uses a combination of bits
seventy-one block lock-bits, a permanent lock-bit ant
WP# pin. to lock and unlock blocks. Block lock-bits gate
block erase, full chip erase and word/byte write
operations. while the permanent lock-bit gates block lock-
bit modification and locked block alternation. Lock-bil
configuration operations (Set Block Lock-Bit, Set
Permanent Lock-Bit and Clear Block Lock-Bits
commands) set and cleared lock-bits.
The status register indicates when the WSM’s block erase.
full chip erase, word/byte write or lock-bit configuration
operation is finished.
The RY/BY# output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software polling) and status masking (interrupt
masking for background block erase, for example). Status
polling using RYiBY# minimizes both CPU overhead and
system power consumption. When low, RY/J3Y# indicates
that the WSM is performing a block erase, full chip erase.
word/byte write or lock-bit configuration. RY/BY#-high 2
indicates that the WSM is ready for a new command.
block erase is suspended (and word/byte write is
inactive), word/byte write is suspended, or the device is in
reset mode.
Rev. 1.25
5 Page 
SHARI=
LHF32JO2
--
9
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.; Read
Information can be read from any block, identifier codes
or status register independent of the Vccw voltage. RP#
can be at V,.
The first task is to write the appropriate read mode
command (Read Array. Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from reset mode. the device automatically
resets to read array mode. Six control pins dictate the data
flow in and out of the component: CE#, OE#, BYTE#,
WE#, RP# and WP#. CE# and OE# must be driven active
to obtain data at the outputs. CE# is the device selection
control. and when active enables the selected memory
device. OE# is the data output (DQo-DQ,,) control and
when active drives the selected memory data onto the I/O
bus. BYTE# is the device I/O interface mde control. WE#
must be at V,,, RP# must be at V,,. and BYTE# and WP#
must be at V, or V,,. Figure 16. 17 illustrates read cycle.
3.2 Output Disable
With OE# at a logic-high level (V,,). the device outputs
Ire disabled. Output pins (DQ,-DQ,j) are placed in a
ligh-impedance state.
3.3 Standby
C1E# at a logic-high level (V,,) places the device in
standby mode which substantially reduces device power
:onsumption. DQ,-DQ,, outputs are placed in a high-
mpedance state independent of OE#. If deselected during
)lock erase. full chip erase. word/byte write or lock-bit
:onfiguration, the device continues functioning, and
:onsuming active power until the operation completes.
3.4 Reset
RP# at V,, initiates the reset mode.
In read modes: RP#-low deselects the memory. places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
1OOns. Time tpHQv is required after return from reset
mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase. full chip erase. word/byte write or
lock-bit configuration modes. RP#-low will abort the
operation. RY/BY# remains low until the reset operation
is complete. Memory contents being altered are no longer
valid; the data may be partially erased or written. Time
tpBwL is required after RP# goes to logic-high (V,,)
before another command can be written.
As with any automated device. it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase. full chip erase, word/byte write or
lock-bit configuration modes. If a CPU reset occurs with
no flash memory reset. proper CPU initialization may not
occur because the flash memory may be providing status
information instead of assay data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal
that resets the system CPU.
Rev. 1.15
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LHF32J02.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LHF32J02 | Flash Memory 32M (2M bb 16/4M bb 8) | Sharp Electrionic Components |
| LHF32J06 | Flash Memory 32M (2M bb 16/4M bb 8) | Sharp Electrionic Components |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |