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PDF LH5PV8512 Data sheet ( Hoja de datos )
| Número de pieza | LH5PV8512 | |
| Descripción | CMOS 4M (512K x 8) Pseudo-Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH5PV8512
CMOS 4M (512K × 8) Pseudo-Static RAM
FEATURES
• 524,288 words × 8 bit organization
• CE access time (tCEA): 120 ns (MAX.)
• Cycle time (tRC): 190 ns (MIN.)
• Power supply:
+3.0 V ± 0.15 V (Operating)
+2.2 V to +3.15 V (Data retention)
• Power consumption (MAX.):
126 mW (Operating)
95 µW (Standby = CMOS input level)
221 µW (Self-refresh = CMOS input level)
• Available for address refresh,
auto-refresh, and self-refresh modes
• 2,048 refresh cycles/32 ms
• Address non-multiple
• Not designed or rated as radiation
hardened
• Package:
32-pin, 525-mil SOP
• Package material: Plastic
• Substrate material: P-type silicon
• Process: Silicon-gate CMOS
• Operating temperature: 0 - 70°C
DESCRIPTION
The LH5PV8512 is a 4M bit Pseudo-Static RAM with
a 524,288 word × 8 bit organization. It is fabricated
using silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo-static operation which elimi-
nates external clock inputs, while having the same
pinout as industry standard SRAMs. Moreover, due to
the functional similarities between PSRAMs and
SRAMs, existing 512K × 8 SRAM sockets can be filled
with the LH5PV8512N with little or no changes. The
advantage is the cost saving realized with the lower
cost PSRAM.
The LH5PV8512 has the ability to fill the gap between
DRAM and SRAM by offering low cost, low power
standby and simple interface.
PIN CONNECTIONS
32-PIN SOP
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
VSS 16
TOP VIEW
32 Vcc
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE/RFSH
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Figure 1. Pin Connections
5PV8512-1
1
1 page  
CMOS 4M (512K × 8) Pseudo-Static RAM
LH5PV8512
AC ELECTRICAL CHARACTERISTICS 1, 2, 3, 4, 5 (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V)
PARAMETER
SYMBOL MIN. MAX. UNIT
NOTES
Random read, write cycle time
Random modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Write disable to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
WE to output in High-Z
OE set up time from CE
OE hold time from CE
OE setup time from chip disable
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write disable
Data setup time from chip disable
Data hold time from write disable
Data hold time from chip disable
Transition time (rise and fall)
Refresh time interval (2,048 cycle)
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto refresh)
Refresh precharge time (Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh precharge
(Self refresh)
tRC
tRMW
tCE
tP
tAS
tAH
tRCS
tRCH
tCEA
tOEA
tCLZ
tOLZ
tWLZ
tCHZ
tOHZ
tWHZ
tOES
tOEH
tOCD
tWP
tWCS
tWCH
tDSW
tDSC
tDHW
tDHC
tT
tREF
tFC
tRFD
tFAP
tFP
tFAS
tFRS
190 ns
250 ns
120 10,000 ns
70 ns
0 ns
6
30 ns
6
0 ns
0 ns
120 ns
7
60 ns
7
20 ns
8
0 ns
8
5 ns
8
0 30 ns
8
30 ns
8
30 ns
8
0 ns
15 ns
0 ns
35 ns
35 10,000 ns
120 10,000 ns
30 ns
9
30 ns
9
0 ns
9
0 ns
9
2 50 ns
32 ms
10, 13, 14
190 ns
70 ns
80 8,000 ns
11, 15
40 ns
8 ms 11, 12, 13, 14, 15
600 ns
DATA RETENTION CHARACTERISTICS 12, 13, 14, 15, 16, 17, 18, 19, 20 (TA = 0 to +70°C)
PARAMETER
SYMBOL MIN. MAX. UNIT
NOTES
Data retention voltage
VR 2.2 3.15 V
Data retention current
(VCC = 3.15 V, CE = VCC - 0.2 V, OE/RFSH = 0.2 V)
ICCDR
70 µA
Refresh setup time
tFS 0 ns
Recover time from data retention mode
tFR 5 ms
5
5 Page 
CMOS 4M (512K × 8) Pseudo-Static RAM
CE
OE/
RFSH
I/O1 - I/O8
NOTE: A0 - A18, WE: Don't Care
tRFD
tFP
tFAS
OPEN
Figure 8. Self-Refresh Cycle
tFRS
LH5PV8512
5PV8512-8
VCC
VCC 2.85 V
VR
OE/RFSH
CE 1.5 V
tFP
tFS
tRFD
DATA RETENTION MODE
tFAS
OE/RFSH ≤ 0.2 V
CE ≥ VCC - 0.2 V
NOTE: A0 - A18, WE = Don't Care
Figure 9. Data Retention Mode
tFRS
tFR
5PV8512-9
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet LH5PV8512.PDF ] | |
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