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PDF LH5PV16256 Data sheet ( Hoja de datos )
| Número de pieza | LH5PV16256 | |
| Descripción | CMOS 4M (256K x 16) Pseudo-Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH5PV16256 CMOS 4M (256K × 16) Pseudo-Static RAM
FEATURES
• 262,144 words × 16 bit organization
• Power supply: +3.0 ± 0.15 V
• Access time: 120 ns (MAX.)
• Cycle time: 190 ns (MIN.)
• Power consumption (MAX.):
126 mW (Operating)
94.5 µW (Standby = CMOS input level)
220.5 µW
(Self-refresh = CMOS input level)
• LVTTL compatible I/O
• Available for address refresh,
auto-refresh, and self-refresh modes
• 2,048 refresh cycles/32 ms
• Address non-multiple
• Available for byte write mode using UWE
and LWE pins
• Package:
44-pin, TSOP (Type II)
• Process: Silicon-gate CMOS
• Operating temperature: 0 - 70°C
• Not designed or rated as radiation
hardened
DESCRIPTION
The LH5PV16256 is a 4M bit Pseudo-Static RAM with
a 262,144 words × 16 bit organization.
PIN CONNECTIONS
44-PIN TSOP (Type II)
TOP VIEW
LWE
UWE
A0
A1
A2
A3
A4
A5
A6
A17
CS
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
CE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 GND
43 I/O15
42 I/O14
41 I/O13
40 I/O12
39 I/O11
38 I/O10
37 I/O9
36 I/O8
35 VCC
34 VCC
33 RFSH
32 I/O7
31 I/O6
30 I/O5
29 I/O4
28 I/O3
27 I/O2
26 I/O1
25 I/O0
24 OE
23 GND
Figure 1. Pin Connections
5PV16256S-1
1
1 page  
CMOS 4M (256 × 16) Pseudo-Static RAM
LH5PV16256
AC ELECTRICAL CHARACTERISTICS 1,2,7 (TA = 0 to +70°C, VCC = 3.0 V ± 0.15 V)
PARAMETER
SYMBOL MIN. MAX. UNIT NOTES
Random read, write cycle time
Random modify write cycle time
CE pulse width
CE precharge time
Address setup time
Row address hold time from CE
Column address hold time from CE
CS setup time from CE
CS hold time from CE
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Write disable to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
WE to output in High-Z
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write disable
Data setup time from chip disable
Data hold time from write disable
Data hold time from chip disable
Data hold time from column address
Column address hold time from chip disable
Column address hold time from write disable
Transition time (rise and fall)
Output disable setup time
Output disable hold time
Refresh time interval (2048 cycle)
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width (Auto refresh)
Refresh precharge time (Auto refresh)
CE delay time from refresh enable
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh precharge
(Self refresh)
VCC recovery time from data retention
Refresh setup hold time
Refresh disable hold time
Chip disable delay time from RFSH
tRC
tRMW
tCE
tP
tAS
tRAH
tCAH
tCSS
tCSH
tRCS
tRCH
tCEA
tOEA
tCLZ
tOLZ
tWLZ
tCHZ
tOHZ
tWHZ
tWCP
tWCS
tWCH
tDSW
tDSC
tDHW
tDHC
tOH
tAHC
tAHW
tT
tODS
tODH
tREF
tFC
tRFD
tFAP
tFP
tFCE
tFAS
tFRS
tR
tFS
tRDH
tRDD
190
250
120
60
0
30
120
0
30
0
0
20
0
0
0
0
0
35
35
120
30
30
0
30
0
20
0
3
0
15
190
90
80
40
190
8,000
600
5
0
15
15
10,000
120
60
30
30
30
10,000
10,000
50
32
1,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
3
3
11
9
4
4
11
9, 13
13
10, 13
12, 13
5, 12, 13
5
5, 11, 13
5
5
5, 13
6
6
8
8
5
5 Page 
CMOS 4M (256 × 16) Pseudo-Static RAM
LH5PV16256
CE VIH
VIL
CS VIH
VIL
RFSH VIH
VIL
A7 - A17
VIH
VIL
OE VIH
VIL
UWE, LWE VIH
VIL
I/O0 - I/O15
VOH
VOL
NOTE: A0 - A6 = Don't Care
tRC
tP tCE
tCSS
tCSH
tAS tRAH
ROW ADDRESS
INPUT
tODS
tRCS
OPEN
tP
tRDH
tODH
tRCH
Figure 8. Address Refresh Cycle
5PV16256S-7
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet LH5PV16256.PDF ] | |
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