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PDF LH5491 Data sheet ( Hoja de datos )
| Número de pieza | LH5491 | |
| Descripción | Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH5481
LH5491
Cascadable 64 × 8 FIFO
Cascadable 64 × 9 FIFO
FEATURES
• Fastest 64 × 8/9 Cascadable FIFO
35/25/15 MHz
• Expandable in Word Width and
FIFO Depth
• Almost-Full/Almost-Empty and
Half-Full Flags
• Fully Independent Asynchronous
Inputs and Outputs
• LH5481 Output Enable forces Data
Outputs to High-Impedance State
• Pin-Compatible Replacements for Cypress
CY7C408A/09A or Logic Devices
L8C408/09 FIFOs
• Industry Standard Pinout
• Packages:
28-Pin, 300-mil DIP
28-Pin PLCC
FUNCTIONAL DESCRIPTION
The LH5481 and LH5491 are high-performance, asyn-
chronous First-In, First-Out (FIFO) memories organized
64 words deep by eight or nine bits wide. The eight-bit
LH5481 has an Output Enable (OE) function, which can
be used to force the eight data outputs (DO) to a high-im-
pedance state. The LH5491 has nine data outputs.
These FIFOs accept eight or nine-bit data at the Data
Inputs (DI). A Shift In (SI) signal writes the DI data into the
FIFO.A Shift Out(SO) signal shifts stored data to the Data
Outputs (DO). The Output Ready (OR) signal indicates
when valid data is present on the DO outputs.
If the FIFO is full and unable to accept more DI data,
Input Ready (IR) will not return HIGH, and SI pulses will
be ignored. If the FIFO is empty and unable to shift data
to the DO outputs, OR will not return HIGH, and SO
pulses will be ignored. The Almost-Full/Almost-Empty
(AFE)flag is asserted (HIGH)when the FIFO is almost-full
(56 words or more)or almost- empty (eight words or less).
The Half-Full (HF) flag is asserted (HIGH) when the FIFO
contains 32 words or more.
Reading and writing operations may be asynchronous,
allowing these FIFOs to be used as buffers between
digital machines of different operating frequencies. The
high speed makes these FIFOs ideal for high perform-
ance communication and controller applications.
PIN CONNECTIONS
28-PIN PDIP
AFE
HF
IR
SI
DI0
DI1
VSS
DI2
DI3
DI4
DI5
DI6
DI7
NC/DI8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
28 VCC
27 MR
26 SO
25 OR
24 DO0
23 DO1
22 VSS
21 DO2
20 DO3
19 DO4
18 DO5
17 DO6
16 DO7
15 OE/DO8
5481-1D
Figure 1. Pin Connections for DIP Package
28-PIN PLCC
TOP VIEW
4 3 2 1 28 27 26
DI0 5
25 OR
DI1 6
24 DO0
VSS 7
23 DO1
DI2 8
22 VSS
DI3 9
21 DO2
DI4 10
20 DO3
DI5 11
19 DO4
12 13 14 15 16 17 18
5481-2D
Figure 2. Pin Connections for PLCC Package
1
1 page  
64 × 8 / 64 × 9 FIFO
LH5481/91
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
SYMBOL
fO
tPHSI
tPLSI
tSSI
tHSI
PARAMETER
Operating Frequency 2
SI HIGH Time 3,8
SI LOW Time 3,8
Data Setup to SI 4
Data Hold from SI 4
15MHz
MIN MAX
15
15
20
–1
14
25MHz
MIN MAX
25
11
18
–1
12
tDLIR
Delay, SI HIGH to IR LOW
20 18
tDHIR
tPHSO
tPLSO
Delay, SI LOW to IR HIGH
SO HIGH Time 3
SO LOW Time 3
24 20
15 11
20 18
tDLOR
Delay, SO HIGH to OR LOW
20 18
tDHOR
Delay, SO LOW to OR HIGH
24 20
tSOR
Data Setup to OR HIGH
–1 –1
tHSO
Data Hold from SO LOW
00
tFT Fallthrough Time
36 34
tBT
tSIR
tHIR
tPIR
tPOR
tDLZOE
tDHZOE
Bubblethrough Time
Data Setup to IR 5
Data Hold from IR 5
Input Ready Pulse HIGH 8
Output Ready Pulse HIGH 8
OE LOW to LOW Z (LH5481) 6,9
OE HIGH to HIGH Z (LH5481) 6,9
28 26
55
55
77
77
35 30
35 30
tDHHF
SI LOW to HF HIGH
40 40
tDLHF
SO LOW to HF LOW
40 40
tDLAFE
SO or SI LOW to AFE LOW
40 40
tDHAFE
SO or SI LOW to AFE HIGH
40 40
tPMR
MR Pulse Width
35 35
tDSI
tDOR
tDIR
tLXMR
MR HIGH to SI HIGH
MR LOW to OR LOW 7
MR LOW to IR HIGH 7
MR LOW to Output LOW 7
25 25
25 25
25 25
25 25
tAFE MR LOW to AFE HIGH
30 30
tHF MR LOW to HF LOW
30 30
tOD SO LOW to Next Data Out Valid
26 22
NOTES:
1. All time measurements performed at ‘AC Test Conditions.’
2. fO = fSI = fSO.
3. tPHSI + tPLSI = tPHSO + tPLSO = I/fO.
4 tSSI and tHSI apply when memory is not full.
5. tSIR and tHIR apply when memory is full and SI is HIGH.
6. High-Z transitions are referenced to the steady-state VOH – 500 mV and VOL + 500 mV levels on the output.
7. After reset goes LOW, all Data outputs will be at LOW level, IR goes HIGH and OR goes LOW.
8. Common dash number devices are guaranteed by design to function properly in a cascaded configuration.
35MHz
MIN MAX
35
9
17
–1
10
16
18
9
17
16
18
–1
0
30
25
5
5
7
7
25
25
36
36
36
36
35
22
20
20
20
30
30
20
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5 Page 
64 × 8 / 64 × 9 FIFO
TIMING DIAGRAMS (cont’d)
MASTER RESET
INPUT READY
OUTPUT READY
SHIFT IN
DATA OUT
HF
AFE
t PMR
t DIR
t DOR
t LXMR
t DHF
t DAFE
t DSI
Figure 13. Master Reset Timing
LH5481/91
5481-13
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LH5491.PDF ] | |
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