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PDF LH543601 Data sheet ( Hoja de datos )
| Número de pieza | LH543601 | |
| Descripción | 256 x 36 x 2 Bidirectional FIFO | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH543601
FEATURES
• Fast Cycle Times: 20/25/30/35 ns
• Pin-Compatible and Functionally-Compatible
0.7µ-Technology Replacement for Sharp LH5420
• Two 256 × 36-bit FIFO Buffers
• Full 36-bit Word Width
• Selectable 36/18/9-bit Word Width on Port B
• Independently-Synchronized (‘Fully-Asynchronous’)
Operation of Port A and Port B
• ‘Synchronous’ Enable-Plus-Clock Control at
Both Ports
• R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
• Synchronous Request/Acknowledge ‘Handshake’
Capability; Use is Optional
• Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
• Asynchronous Output Enables
• Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
• Almost-Full Flag and Almost-Empty Flag are
Programmable
• Mailbox Registers with Synchronized Flags
• Data-Bypass Function
• Data-Retransmit Function
• Automatic Byte Parity Checking
• 8 mA-IOL High-Drive Three-State Outputs with
Built-In Series Resistor
• TTL/CMOS-Compatible I/O
• Space-Saving PQFP and TQFP Packages
• PQFP to PGA Package Conversion 1
256 × 36 × 2 Bidirectional FIFO
FUNCTIONAL DESCRIPTION
The LH543601 contains two FIFO buffers, FIFO #1
and FIFO #2. These operate in parallel, but in opposite
directions, for bidirectional data buffering. FIFO #1 and
FIFO #2 each are organized as 256 by 36 bits. The
LH543601 is ideal either for wide unidirectional applica-
tions or for bidirectional data applications; component
count and board area are reduced.
The LH543601 has two 36-bit ports, Port A and Port B.
Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edge-
sampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH543601 is a fully-static
part.
Conceptually, the port clocks CKA and CKB are free-
running, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ wave-
forms must be periodic. An ‘asynchronous’ mode of
operation is possible, in one or both directions, inde-
pendently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic ‘clock’
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for each
FIFO. The Almost-Full and Almost-Empty flags are pro-
grammable over the entire FIFO depth, but are automat-
ically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.
NOTE:
1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics’ SMT/PGA Generic
Converter model #5853.® This converter maps the LH543601
132-pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil
pitch). For more information, contact Sharp or ITT Pomona
Electronics at 1500 East Ninth Street, Pomona, CA 91766,
(909) 469-2900.
1
1 page  
256 × 36 × 2 Bidirectional FIFO
WRITE
PORT A
I/O
READ
FIFO 1
FIFO 2
READ
PORT B
I/O
WRITE
PORT A
CONTROL
PORT B
CONTROL
Figure 3a. Simplified LH543601 Block Diagram
LH543601
543601-36
RS
MBF2
A2A
A1A
A0A
CKA
R/WA
ENA
REQA
ACKA
FF1
AF1
HF1
RT2
EF2
AE2
RESET
LOGIC
COMMAND
PORT AND
REGISTER
PORT A
SYNCH-
RONOUS
CONTROL
LOGIC
OEA
D0A - D35A
PORT A
I/O
PFA
PARITY
CHECKING
BYPASS
MAILBOX
REGISTER
#1
MAILBOX
REGISTER
#2
FIFO #1
MEMORY ARRAY
256 x 36
WRITE
POINTER
READ
POINTER
FIXED AND
PROGRAMMABLE
STATUS FLAGS
FIXED AND
PROGRAMMABLE
STATUS FLAGS
READ
POINTER
WRITE
POINTER
FIFO #2
MEMORY ARRAY
256 x 36
RESOURCE
REGISTERS
COMMAND
PORT AND
REGISTER
PORT B
SYNCH-
RONOUS
CONTROL
LOGIC
PORT B
I/O
PARITY
CHECKING
Figure 3b. Detailed LH543601 Block Diagram
MBF1
A0B
CKB
R/WB
ENB
REQB
ACKB
EF1
AE1
RT1
FF2
AF2
HF2
OEB
D0B - D35B
WS0, WS1
PFB
543601-6
5
5 Page 
256 × 36 × 2 Bidirectional FIFO
LH543601
OPERATIONAL DESCRIPTION (cont’d)
becomes valid on the data-bus pins (D0A – D35A or
D0B – D35B) by a time tA after the rising clock (CKA or
CKB) edge, provided that the data outputs are enabled.
OEA and OEB are assertive-LOW, asynchronous, Out-
put Enable control input signals. Their effect is only to
enable or disable the output drivers of the respective port.
Disabling the outputs does not disable a read operation;
data transmitted to the corresponding output register will
remain available later, when the outputs again are en-
abled, unless it subsequently is overwritten.
When an empty condition is reached, read operations
are locked out until a valid write operation(s) has loaded
additional data into the FIFO. Following the first write to
an empty FIFO, the corresponding empty flag (EF) will be
deasserted (HIGH). The first read operation should begin
no earlier than a First Read Latency (tFRL) after the first
write to an empty FIFO, to ensure that correct read data
words are retrieved.
Dedicated FIFO Status Flags
Six dedicated FIFO status flags are included for Full
(FF1 and FF2), Half-Full (HF1 and HF2), and Empty (EF1
and EF2). FF1, HF1, and EF1 indicate the status of FIFO
#1; and FF2, HF2, and EF2 indicate the status of FIFO #2.
A Full Flag is asserted following the first subsequent
rising clock edge for a write operation which fills the FIFO.
A Full Flag is deasserted following the first subsequent
falling clock edge for a read operation to a full FIFO. A
Half-Full Flag is updated following the first subsequent
rising clock edge of a read or write operation to a FIFO
which changes its ‘half-full’ status. An Empty Flag is
asserted following the first subsequent rising clock edge
for a read operation which empties the FIFO. An Empty
Flag is deasserted following the falling clock edge for a
write operation to an empty FIFO.
Programmable Status Flags
Four programmable FIFO status flags are provided,
two for Almost-Full (AF1 and AF2), and two for Almost-
Empty (AE1 and AE2). Thus, each port has two program-
mable flags to monitor the status of the two internal FIFO
buffer memories. The offset values for these flags are
initialized to eight locations from the respective FIFO
boundaries during reset, but can be reprogrammed over
the entire FIFO depth.
An Almost-Full Flag is asserted following the first sub-
sequent rising clock edge after a write operation which
has partially filled the FIFO up to the ‘almost-full’ offset
point. An Almost-Full Flag is deasserted following the first
subsequent falling clock edge after a read operation
which has partially emptied the FIFO down past the
‘almost-full’ offset point. An Almost-Empty Flag is as-
serted following the first subsequent rising clock edge
after a read operation which has partially emptied the
FIFO down to the ‘almost-empty’ offset point. An Almost-
Empty Flag is deasserted following the first subsequent
falling clock edge after a write operation which has par-
tially filled the FIFO up past the ‘almost-empty’ offset
point.
Flag offsets may be written or read through the Port A
data bus. All four programmable FIFO status flag offsets
can be set simultaneously through a single 36-bit status
word; or, each programmable flag offset can be set
individually, through one of four eight-bit status words.
Table 3 illustrates the data format for flag-programming
words .
Also, Table 4 defines the meaning of each of the five
flags, both the dedicated flags and the programmable
flags, for the LH543601.
WARNING: Control inputs which may affect the compu-
tation of flag values at a port generally should not change
while the clock for that port is HIGH, since some updating
of flag values takes place on the falling edge of the clock.
Mailbox Operation
Two mailbox registers are provided for passing system
hardware or software control/status words between ports.
Each port can read its own mailbox and write to the other
port’s mailbox. Mailbox access is performed on the rising
edge of the controlling FIFO’s clock, with the mailbox
address selected and the enable (ENA or ENB) HIGH.
That is, writing to Mailbox Register #1, or reading from
Mailbox Register #2, is synchronized to CKA; and writing
to Mailbox Register #2, or reading from Mailbox Register
#1, is synchronized to CKB.
The R/WA/B and OEA/B pins control the direction and
availability of mailbox-register accesses. Each mailbox
register has its own New-Mail-Alert Flag (MBF1 and
MBF2), which is synchronized to the reading port’s clock.
These New-Mail-Alert Flags are status indicators only,
and cannot inhibit mailbox-register read or write operations.
Request Acknowledge Handshake
A synchronous request-acknowledge handshake fea-
ture is provided for each port, to perform boundary syn-
chronization between asynchronously-operated ports.
The use of this feature is optional. When it is used, the
Request input (REQA/B) is sampled at a rising clock edge.
With REQA/B HIGH, R/WA/B determines whether a FIFO
read operation or a FIFO write operation is being re-
quested. The Acknowledge output (ACKA/B) is updated
during the following clock cycle(s). ACKA/B meets the
setup and hold time requirements of the Enable input
(ENA or ENB). Therefore, ACKA/B may be tied back to the
enable input to directly gate FIFO accesses, at a slight
decrease in maximum operating frequency.
The assertion of ACKA/B signifies that REQA/B was
asserted. However, ACKA/B does not depend logically on
ENA/B; and thus the assertion of ACKA/B does not prove
that a FIFO write access or a FIFO read access actually
took place. While REQA/B and ENA/B are being held
HIGH, ACKA/B may be considered as a synchronous,
predictive boundary flag. That is, ACKA/B acts as a syn-
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH543601.PDF ] | |
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