PDF LH540204 Data sheet ( Hoja de datos )

Número de pieza	LH540204
Descripción	CMOS 4096 x 9 Asynchronous FIFO
Fabricantes	Sharp Electrionic Components
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No Preview Available ! LH540204 FEATURES • Fast Access Times: 20/25/35/50 ns • Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology • Input Port and Output Port Have Entirely Independent Timing • Expandable in Width and Depth • Full, Half-Full, and Empty Status Flags • Data Retransmission Capability • TTL-Compatible I/O • Pin and Functionally Compatible with Sharp LH5499 and with Am/IDT/MS7204 • Control Signals Assertive-LOW for Noise Immunity • Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC PIN CONNECTIONS 28-PIN PDIP 28-PIN SOJ * W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TOP VIEW 28 VCC 27 D4 26 D5 25 D6 24 D7 23 FL/RT 22 RS 21 EF 20 XO/HF 19 Q7 18 Q6 17 Q5 16 Q4 15 R 540204-2D Figure 1. Pin Connections for PDIP and SOJ * Packages CMOS 4096 × 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION The LH540204 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAMtech- nology, capable of storing up to 4096 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540204 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. The input and output ports operate entirely inde- pendently of each other, unless the LH540204 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, as- sertive-LOW control inputs: Write (W) for data entry at the input port, or Read (R) for data retrieval at the output port. Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwise might occur either by attempting to write additional words into an already-full LH540204, or by attempting to read additional words from an already-empty LH540204. When an LH540204 is operating in a depth-cascaded configuration, the Half-Full Flag is not available. 32-PIN PLCC TOP VIEW 4 3 2 1 32 31 30 D2 5 D1 6 D0 7 XI 8 29 D6 28 D7 27 NC 26 FL/RT FF 9 25 RS Q0 10 24 EF Q1 11 23 XO/HF NC 12 22 Q7 Q2 13 21 Q6 14 15 16 17 18 19 20 NOTE: * = No external electrical connections are allowed. 540204-3D Figure 2. Pin Connections for PLCC Package * This is a final data sheet; except that all references to the SOJ package have Advance Information status. 1 1 page CMOS 4096 × 9 Asynchronous FIFO OPERATIONAL MODES Standalone Configuration When depth cascading is not required for a given application, the LH540204 is placed in standalone mode by tying the Expansion In input (XI) to ground. This input is internally sampled during a reset operation. (See Table 1.) LH540204 Width Expansion Word-width expansion is implemented by placing mul- tiple LH540204 devices in parallel. Each LH540204 should be configured for standalone mode. In this ar- rangement, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any one device. In practice, it is better to derive ‘composite’ flag values using external logic, since there may be minor speed variations between different actual devices. (See Figures 4, 5, and 6.) WRITE DATA IN D0 - D8 FULL FLAG RESET HF W 9 FF LH540204 RS XI R 9 EF RT READ DATA OUT Q0 - Q8 EMPTY FLAG RETRANSMIT Figure 4. Standalone FIFO (4096 × 9) 540204-17 DATA IN D0 - D17 18 WRITE FULL FLAG RESET 9 W FF RS HF LH540204 XI R RT 9 HF 9 W LH540204 RS XI EF R RT 9 Figure 5. FIFO Word-Width Expansion (4096 × 18) EMPTY FLAG READ RETRANSMIT 18 DATA OUT Q0 - Q17 540204-18 5 5 Page CMOS 4096 × 9 Asynchronous FIFO TIMING DIAGRAMS tRSC tRS RS R,W EF t RRSS t WRSS tEFL tRSR tFFH , tHFH FF,HF NOTES: 1. tRSC = tRS + tRSR. 2. W and R ≥ VIH around the rising edge of RS. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 10. Reset Timing R Q0 - Q8 W D0 - D8 tRC t A tRR t RPW tA t RLZ t DV VALID DATA OUT t WPW t WC t WR t RHZ VALID DATA OUT t DS t DH VALID DATA IN VALID DATA IN Figure 11. Asynchronous Write and Read Operation LH540204 540204-14 540204-5 11 11 Page

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