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PDF LH532100B-1 Data sheet ( Hoja de datos )
| Número de pieza | LH532100B-1 | |
| Descripción | CMOS 2M (256K x 8) MROM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH532100B-1
CMOS 2M (256K × 8) MROM
FEATURES
• 262,144 words × 8 bit organization
• Access time: 120 ns (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Power consumption:
Operating: 275 mW (MAX.)
Standby: 550 µW (MAX.)
• Mask-programmable control pin:
Pin 1 = OE1/OE1/DC
Pin 24 = OE/OE
• Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 450-mil QFJ (PLCC)
32-pin, 8 × 20 mm2 TSOP (Type I)
32-pin, 400-mil TSOP (Type II)
DESCRIPTION
The LH532100B-1 is a CMOS 2M-bit mask-program-
mable ROM organized as 262,144 × 8 bits. It is fabri-
cated using silicon-gate process technology.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
OE1/OE1/DC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TOP VIEW
32 VCC
31 DC
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE/OE
23 A10
22 CE
21 D7
20 D6
19 D5
18 D4
17 D3
532100B1-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN QFJ
TOP VIEW
D7
CE
A10
OE/OE
A11
A9
A8
A13
A14
20 19 18 17 16 15 14
21 13
22 12
23 11
24 10
25 9
26 8
27 7
28 6
29 5
30 31 32 1 2 3 4
D0
A0
A1
A2
A3
A4
A5
A6
A7
532100B1-7
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
1 page  
CMOS 2M MROM
LH532100B-1
AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read cycle time
tRC 120
Address access time
tAA
120
Chip enable access time
tACE
120
Output enable delay time
tOE
50
Output hold time
tOH 10
CE to output in High-Z
OE to output in High-Z
tCHZ
tOHZ
50
ns
ns
ns
ns
ns
ns
NOTE:
1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
RATING
0.6 V to 2.4 V
10 ns
1.5 V
0.8 V and 2.2 V
1 TTL + 100 pF
NOTE
1
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
tRC
A0 - A17
CE
OE/OE1
OE/OE1
tAA
(NOTE)
tACE
(NOTE)
tOE
(NOTE)
tCHZ
tOHZ
tOH
D0 - D7
DATA VALID
NOTE: The output data becomes valid when the
last intervals, tAA, tACE, or tOE, have concluded.
Figure 6. Timing Diagram
532100B1-5
5
5 Page | ||
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| PDF Descargar | [ Datasheet LH532100B-1.PDF ] | |
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