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PDF LH532000B Data sheet ( Hoja de datos )
| Número de pieza | LH532000B | |
| Descripción | CMOS 2M (256K x 8/128K x 16) MROM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH532000B
CMOS 2M (256K × 8/128K × 16) MROM
FEATURES
• 262,144 words × 8 bit organization
(Byte mode)
131,072 words × 16 bit organization
(Word mode)
• BYTE input pin selects bit configuration
• Access times: 120/150 ns (MAX.)
• Low-power consumption:
Operating: 275 mW (MAX.)
Standby: 550 µW (MAX.)
• Programmable OE/OE and OE1/OE1/DC
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
48-pin, 12 × 18 mm2 TSOP (Type I)
• ×16 word-wide pinout
DESCRIPTION
The LH532000B is a 2M-bit mask-programmable
ROM with two programmable memory organizations,
byte and word modes. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
TOP VIEW
OE1/OE1/DC
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE/OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A8
39 A9
48 A10
37 A11
36 A12
35 A13
34 A14
33 A15
32 A16
31 BYTE
30 GND
29 D15/A-1 (LSB)
28 D7
27 D14
26 D6
25 D13
24 D5
23 D12
22 D4
21 VCC
532000B-1
Figure 1. Pin Connections for DIP and
SOP Packages
1
1 page  
CMOS 2M MROM
LH532000B
AC CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C)
PARAMETER
SYMBOL
120 ns
MIN.
MAX.
150 ns
MIN.
MAX.
Read cycle time
tRC 120
150
Address access time
tAA
120 150
Chip enable access time
tACE
120
150
Output enable delay time
tOE
55
70
Output hold time
tOH 5
10
CE to output in High-Z
tCHZ
55
70
OE to output in High-Z
tOHZ
55
70
NOTE:
1. This is the time required for the output to become high-impedance.
AC TEST CONDITIONS
PARAMETER
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
RATING
0.6 V to 2.4 V
10 ns
1.5 V
0.8 V and 2.2 V
1TTL +100 pF
UNIT
ns
ns
ns
ns
ns
ns
ns
NOTE
1
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the VCC pin and the GND pin.
(NOTE 2)
A-1 - A16
(A0 - A16)
tRC
tAA(NOTE 1)
CE
tACE
tCHZ
OE/OE1
OE/OE1
(NOTE 2)
D0 - D7
(D0 - D15)
tOE (NOTE 1)
NOTES:
1. Data becomes valid after tAA, tACE, and tOE from address
input, chip enable or output enable, respectively have been met.
2. Applied to byte mode. Signals in parentheses apply to word mode.
tOHZ
DATA VALID
tOH
Figure 4. Timing Diagram
532000B-3
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LH532000B.PDF ] | |
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