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PDF LH52258A Data sheet ( Hoja de datos )
| Número de pieza | LH52258A | |
| Descripción | CMOS 32K x 8 Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH52258A
CMOS 32K × 8 Static RAM
FEATURES
• Fast Access Times: 20/25 ns
• Low-Power Standby when Deselected
• TTL Compatible I/O
• 5 V ± 10% Supply
• Fully-Static Operation
• JEDEC Standard Pinout
• Packages:
28-Pin, 300-mil DIP
28-Pin, 300-mil SOJ
FUNCTIONAL DESCRIPTION
The LH52258A is a high-speed 262,144 bit static RAM
organized as 32K × 8. A fast, efficient design is obtained
with a CMOS periphery and a matrix constructed with
polysilicon load memory cells.
This RAM is fully static in operation. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH). Standby power (ISB1) drops
to its lowest level if E is raised to within 0.2 V of VCC.
Write cycles occur when both Chip Enable (E) and
Write Enable (W) are LOW. Data is transferred from the
DQ pins to the memory location specified by the 15
address lines. The proper use of the Output Enable
control (G) can prevent bus contention.
When E is LOW and W is HIGH, a static Read will
occur at the memory location specified by the address
lines. G must be brought LOW to enable the outputs.
Since the device is fully static in operation, new Read
cycles can be performed by simply changing the address.
High-frequency design techniques should be em-
ployed to obtain the best performance from this device.
Solid, low-impedance power and ground planes, with
high-frequency decoupling capacitors, are recom-
mended. Series termination of the inputs should be con-
sidered when transmission line effects occur.
PIN CONNECTIONS
28-PIN DIP
28-PIN SOJ
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
28 VCC
27 W
26 A13
25 A8
24 A9
23 A11
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
52258A-1D
Figure 1. Pin Connections for DIP and
SOJ Packages
1
1 page  
CMOS 32K × 8 Static RAM
LH52258A
AC ELECTRICAL CHARACTERISTICS 1 (Over Operating Range)
SYMBOL
DESCRIPTION
–20
MIN MAX
–25
MIN MAX
UNITS
READ CYCLE
tRC Read Cycle Time
tAA Address Access Time
tOH Output Hold from Address Change
tEA E Low to Valid Data
tELZ E Low to Output Active 2,3
tEHZ E High to Output High-Z 2,3
tGA G Low to Valid Data
tGLZ G Low to Output Active 2,3
tGHZ G High to Output High-Z 2,3
tPU E Low to Power Up Time 3
tPD E High to Power Down Time 3
20 25 ns
20 25 ns
4 4 ns
20 25 ns
4 4 ns
0 10 0 12 ns
10 12 ns
0 0 ns
0 9 0 10 ns
0 0 ns
25 30 ns
WRITE CYCLE
tWC Write Cycle Time
20 25 ns
tEW E Low to End of Write
15 20 ns
tAW Address Valid to End of Write
15 20 ns
tAS Address Setup
0 0 ns
tAH Address Hold from End of Write
0 0 ns
tWP W Pulse Width
12 15 ns
tDW Input Data Setup Time
10 12 ns
tDH
tWHZ
tWLZ
Input Data Hold Time
W Low to Output High-Z 2,3
W High to Output Active 2,3
0 0 ns
8 10 ns
0 0 ns
NOTES:
1. AC Electrical Characteristics specified at ‘AC Test Conditions’ levels.
2. Active output to High-Z and High-Z to output active tests specified for a ±500 mV transition from steady state levels into the test load. The test
load has 5 pF capacitances.
3. Guaranteed by design but not tested.
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet LH52258A.PDF ] | |
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