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PDF LH521028 Data sheet ( Hoja de datos )
| Número de pieza | LH521028 | |
| Descripción | CMOS 64K x 18 Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH521028
CMOS 64K × 18 Static RAM
FEATURES
• Fast Access Times: 17/20/25/35 ns
• Wide Word (18-Bits) for:
– Improved Performance
– Reduced Component Count
– Nine-bit Byte for Parity
• Transparent Address Latch
• Reduced Loading on Address Bus
• Low-Power Stand-by Mode when
Deselected
• TTL Compatible I/O
• 5 V ± 10% Supply
• 2 V Data Retention
• JEDEC Standard Pinout
• Package: 52-Pin PLCC
FUNCTIONAL DESCRIPTION
The LH521028 is a high-speed 1,179,648-bit CMOS
SRAM organized as 64K × 18. A fast, efficient design is
obtained with a CMOS periphery and a matrix con-
structed with polysilicon load memory cells. The
LH521028 is available in a compact 52-Pin PLCC, which
along with the six pairs of supply terminals, provide for
reliable operation.
The control signals include Write Enable (W), Chip
Enable (E), High and Low Byte Select (SL and SH), Output
Enable (G) and Address Latch Enable (ALE). The wide
word provides for reduced component count, improved
density, reduced Address bus loading and improved per-
formance. The wide word also allows for byte-parity with
no additional RAM required.
This RAM is fully static in operation. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH).The Byte-select controls, SH
and SL, are also used to enable or disable Read and Write
operations on the high and the low bytes. The Address
Latches are transparent when ALE is HIGH (for applica-
tions not requiring a latch), and are latched when ALE is
LOW. The Address Latches and the wide word help to
eliminate the need for external Addressbusbuffers and/or
latches.
Write cycles occur when Chip Enable (E), SH and/or
SL, and Write Enable (W) are LOW. The Byte-select
signals can be used for Byte-write operations by disabling
the other byte during the Write operation. Data is trans-
ferred from the DQ pins to the memory location specified
by the 16 address lines. The proper use of the Output
Enable control (G) can prevent bus contention.
When E and either SH or SL are LOW and W is HIGH,
a static Read will occur at the memory location specified
by the address lines. G must be brought LOW to enable
the outputs. Since the device is fully static in operation,
new Read cycles can be performed by simply changing
the address with ALE HIGH.
PIN CONNECTIONS
52-PIN PLCC
TOP VIEW
DQ9
DQ10
VCC
VSS
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
7 6 5 4 3 2 1 52 51 50 49 48 47
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 26 27 28 29 30 31 32 33
46 DQ8
45 DQ7
44 DQ6
43 VCC
42 VSS
41 DQ5
40 DQ4
39 DQ3
38 DQ2
37 VSS
36 VCC
35 DQ1
34 DQ0
521028-1D
Figure 1. Pin Connections for PLCC Package
4-211
1 page  
CMOS 64K × 18 Static RAM
LH521028
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
RATING
VCC to VSS Potential
Input Voltage Range
DC Output Current 2
Storage Temperature Range
–0.5 V to 7 V
–0.5 V to VCC + 0.5 V
± 40 mA
–65oC to 150oC
Power Dissipation (Package Limit) 2 W
NOTES:
1. Stresses greater than those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress rating for
transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ‘Operating Range’
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time.
OPERATING RANGES
SYMBOL
PARAMETER
MIN TYP
TA Temperature, Ambient 0
VCC Supply Voltage
4.5 5.0
VSS Supply Voltage
00
VIL
Logic ‘0’ Input Voltage 1
– 0.5
VIH Logic ‘1’ Input Voltage 2.2
NOTE:
1. Negative undershoot of up to 3.0 V is permitted once per cycle.
MAX
70
5.5
0
0.8
VCC + 0.5
UNIT
oC
V
V
V
V
DC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
ICC1 Operating Current 1
TEST CONDITIONS
tCYCLE = minimum
MIN TYP MAX UNIT
300 mA
ISB1 Standby Current
E ≥ VCC – 0.2 V
VIN ≥ VCC – 0.2 V or VIN ≤ 0.2 V
f=0
4 mA
ISB2 Standby Current
E ≥ VIH
VIN = VIH or VIL
50 mA
ILI Input Leakage Current VIN = 0 V to VCC
–2 2 µA
ILO
I/O Leakage Current
VIN = 0 V to VCC
–2 2 µA
VOH Output High Voltage IOH = –4.0 mA 2.4 V
VOL Output Low Voltage IOL = 8.0 mA
0.4 V
NOTE:
1. ICC is dependent upon output loading and cycle rates. Specified values are with outputs open.
4-215
5 Page 
CMOS 64K × 18 Static RAM
LH521028
TIMING DIAGRAMS – WRITE CYCLE
Addresses must be stable during unlatched Write
cycles. The outputs will remain in the High-Z state if W is
LOW when E and SH / SL go LOW. If G is HIGH, the
outputs will remain in the High-Z state. Although these
examples illustrate timing with G active, it is recom-
mended that G be held HIGH for all Write cycles. This will
prevent the LH521028’s outputs from becoming active,
preventing bus contention, thereby reducing system
noise.
Write Cycle No. 1 (Unlatched W Controlled Write)
Chip is selected: E, G, and SH / SL are LOW, ALE is
High. Using only W to control Write cycles may not offer
the best performance since both tWHZ and tDW timing
specifications must be met.
Write Cycle No. 2 (E, SL, SH Controlled Write)
G is LOW. DQ lines may transition to Low-Z if the falling
edge of W occurs after the falling edge of E, SH/SL if G is
LOW.
ADDRESS
W
DQ
ADDRESS
E, SL, SH
W
DQ
tWC
VALID ADDRESS
tAW tAH
tAS tWP
tWHZ
PREVIOUS OUTPUT
tDW
VALID DATA
tWLZ
tDH
Figure 8. Write Cycle No. 1
tWC
VALID ADDRESS
tEW
tAS tWP tAH
tELZ
tWHZ
tDW
VALID DATA
tDH
Figure 9. Write Cycle No. 2
521028-6
521028-7
4-221
11 Page | ||
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