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PDF LH5164ASH Data sheet ( Hoja de datos )
| Número de pieza | LH5164ASH | |
| Descripción | CMOS 64K (8K x 8) Static RAM | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH5164ASH
CMOS 64K (8K × 8) Static RAM
FEATURES
• 8,192 × 8 bit organization
• Access time: 500 ns (MAX.)
• Power consumption:
Operating:
60 mW (MAX.) @ 3 V
Standby:
3 µW (MAX.) @ 70°C @ 3 V
9 µW (MAX.) @ 85°C @ 3 V
• Fully-static operation
• Three-state outputs
• Wide operating voltage range:
2.5 V to 5.5 V
• TTL compatible I/O
• Wide temp. range
tOPR: -40 to +85°C
• Packages:
28-pin, 450-mil SOP
28-pin, 8 × 13 mm2 TSOP (Type I)
DESCRIPTION
The LH5164ASH is a static RAM organized as
8,192 × 8 bits. It is fabricated using silicon-gate CMOS
process technology.
It is designed for 2.5 to 5.5 V low voltage operation
and wide temperature range from -40 to +85°C.
PIN CONNECTIONS
28-PIN SOP
TOP VIEW
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 CE2
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE1
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
5164ASH-1
Figure 1. Pin Connections for SOP Package
28-PIN TSOP (Type I)
OE
A11
A9
A8
CE2
WE
VCC
NC
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
28 A10
27 CE1
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 GND
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
5164ASH-8
Figure 2. Pin Connections for TSOP Package
1
1 page  
CMOS 64K (8K × 8) Static RAM
LH5164ASH
DATA RETENTION CHARACTERISTICS (TA = -40 to +85°C)
PARAMETER
Data retention supply voltage
Data retention supply current
SYMBOL
VCCDR
ICCDR
CONDITIONS
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
VCCDR = 3 V,
CE2 ≤ 0.2 V or
CE1 ≥ VCCDR – 0.2 V
TA = 25°C
TA = 40°C
Chip disable to data retention
tCDR
Recovery time
tR
NOTES:
1. CE2 should be ≥ VCCDR - 0.2 V or ≤ 0.2 V when CE1 ≥ VCCDR - 0.2 V.
2. tRC = Read cycle time
MIN.
2.0
0
tRC
MAX.
5.5
0.2
0.4
0.6
UNIT NOTE
V1
µA
µA 1
µA
ns
ns 2
CE1 CONTROL (NOTE)
VCC
2.5 V
VCC - 0.5 V
VCCDR
CE1
0V
tCDR
DATA RETENTION MODE
CE1 ≥ VCCDR - 0.2 V
tR
CE2 CONTROL
VCC
CE2
2.5 V
DATA RETENTION MODE
tCDR
tR
VCCDR
0.2 V
0V
CE2 ≥ 0.2 V
NOTE: To control data hold at CE1, fix the input level of CE2 between VCCDR to VCCDR - 0.2 V or 0 V to 0.2 V
during the data retention.
Figure 4. Low Voltage Data Retention
5164ASH-6
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet LH5164ASH.PDF ] | |
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