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PDF ADC774 Data sheet ( Hoja de datos )
| Número de pieza | ADC774 | |
| Descripción | Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown | |
| Logotipo |  |
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® ADC774
www.DataSheet4U.com
Microprocessor-Compatible
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q COMPLETE 12-BIT A/D CONVERTER WITH
REFERENCE, CLOCK, AND 8-, 12-, or 16-
BIT MICROPROCESSOR BUS INTERFACE
q ALTERNATE SOURCE FOR HI774 A/D
CONVERTER: 8.5µs Conversion Time,
150ns Bus Access Time
q FULLY SPECIFIED FOR OPERATION ON
±12V OR ±15V SUPPLIES
q NO MISSING CODES OVER
TEMPERATURE:
0°C to +75°C: ADC774J, K
–55°C to +125°C: ADC774SH, TH
DESCRIPTION
The ADC774 is a 12-bit successive approximation
analog-to-digital converter, utilizing state-of-the-art
CMOS and laser-trimmed bipolar die custom-designed
for freedom from latch-up and for optimum AC per-
formance. It is complete with a self-contained +10V
reference, internal clock, digital interface for micropro-
cessor control, and three-state outputs.
The reference circuit, containing a buried zener, is laser-
trimmed for minimum temperature coefficient. The
clock oscillator is current-controlled for excellent sta-
bility over temperature. Full-scale and offset errors may
be externally trimmed to zero. Internal scaling resistors
are provided for the selection of analog input signal
ranges of 0V to +10V, 0V to +20V, ±5V, and ±10V.
The converter may be externally programmed to pro-
vide 8- or 12-bit resolution. The conversion time for 12
bits is factory set for 8.5µs maximum.
Output data are available in a parallel format from TTL-
compatible three-state output buffers. Output data are
coded in straight binary for unipolar input signals and
bipolar offset binary for bipolar input signals.
The ADC774, available in both industrial and military
temperature ranges, requires supply voltages of +5V
and ±12V or ±15V. It is packaged in a 28-pin plastic
DIP, or a hermetic side-brazed ceramic DIP.
Control
Inputs
Bipolar
Offset
20V Range
10V Range
Reference
Input
Reference
Output
Control Logic
Clock
Comparator
12-Bit D/A
Converter
10V
Reference
Status
Parallel
Data
Output
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1988 Burr-Brown Corporation
PDS-835E
Printed in U.S.A. March, 1992
1 page  
CONTROLLING THE ADC774
This is an abridged data sheet. For Discussion of Specifica-
tions, Installation, Calibration refer to ADC574A data sheet
or order PDS-835.
The Burr-Brown ADC774 can be easily interfaced to most
microprocessor systems and other digital systems. The
microprocessor may take full control of each conversion, or
the converter may operate in a stand-alone mode, controlled
only by the R/C input. Full control consists of selecting an
8- or 12-bit conversion cycle, initiating the conversion, and
reading the output data when ready—choosing either 12 bits
all at once, or 8 bits followed by 4 bits in a left-justified
format. The five control inputs (12/8, CS, AO, R/C, and CE)
are all TTL-/CMOS-compatible. The functions of the con-
www.DataSheet4U.comtrol inputs are described in Table I. The control function
truth table is listed in Table II.
Read footnote 5 to the Electrical Specifications table if
using ADC774 to replace the HI-774.
Conversion is initiated by a high-to-low transition of R/C.
The three-state data output buffers are enabled when R/C is
high and STATUS is low. Thus, there are two possible
modes of operation; conversion can be initiated with either
positive or negative pulses. In either case the R/C pulse
must remain low for a minimum of 50ns.
R/C tHRL
tDS
STS
DB11–DB0
Data Valid
tC
tHDR High-Z State
tHS
Data Valid
FIGURE 1. R/C Pulse Low—Outputs Enabled After Con-
version.
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is ac-
complished by a single control line connected to R/C. In this
mode CS and AO are connected to digital common and CE
and 12/8 are connected to VLOGIC (+5V). The output data
are presented as 12-bit words. The stand-alone mode is used
in systems containing dedicated input ports which do not
require full bus interface capability.
R/C
tHRH
tDS
STS
DB11–
DB0
tDDR
High-Z
Data Valid
tHDR
tC
High-Z State
FIGURE 2. R/C Pulse High—Outputs Enabled Only While
R/C Is High.
PIN
DESIGNATION
DEFINITION
FUNCTION
CE (Pin 6)
CS (Pin 3)
R/C (Pin 5)
AO (Pin 4)
12/8 (Pin 2)
Chip Enable
(active high)
Chip Select
(active low)
Read/Convert
(“1” = read)
(“0” = convert)
Byte Address
Short Cycle
Data Mode Select
(“1” = 12 bits)
(“0” = 8 bits)
Must be high (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
conversion.
Must be low (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate
a conversion.
Must be low (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a
conversion. Must be high (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
In the start-convert mode, AO selects 8-bit (AO = “1”) or 12-bit (AO = “0”) conversion mode. When reading
output data in two 8-bit bytes, AO = “0” accesses 8 MSBs (high byte) and AO = “1” accesses 4 LSBs and
trailing “0s” (low byte).
When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the
MSBs or LSBs as determined by the AO line.
TABLE I. ADC774 Control Line Functions.
CE CS
0X
X1
0
0
1
1
10
10
10
10
10
R/C 12/8
XX
XX
0X
0X
0X
0X
X
X
11
10
10
AO OPERATION
X None
X None
0 Initiate 12-bit conversion
1 Initiate 8-bit conversion
0 Initiate 12-bit conversion
1 Initiate 8-bit conversion
0 Initiate 12-bit conversion
1 Initiate 8-bit conversion
X Enable 12-bit output
0 Enable 8 MSBs only
1 Enable 4 LSBs plus 4
trailing zeros
TABLE II. Control Input Truth Table.
SYMBOL PARAMETER
MIN TYP
tHRL Low R/C Pulse Width
50
tDS STS Delay from R/C
tHDR Data Valid After R/C Low
25
tHS STS Delay After Data Valid
150
tHRH High R/C Pulse Width
150
tDDR Data Access Time
TABLE III. Stand-Alone Mode Timing.
MAX
200
375
150
UNITS
ns
ns
ns
ns
ns
ns
®
5 ADC774
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