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PDF LH28F400SUB-Z0 Data sheet ( Hoja de datos )
| Número de pieza | LH28F400SUB-Z0 | |
| Descripción | 4M (512K bb 8/ 256K bb 16) Flash Memory | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH28F400SUB-Z0
4M (512K × 8, 256K × 16)
Flash Memory
FEATURES
• User-Configurable x8 or x16 Operation
• 5 V Write/Erase Operation
(5 V VPP, 3.3 V VCC)
– No Requirement for DC/DC Converter to
Write/Erase
• 150 ns Maximum Access Time
(VCC = 3.3 V ± 0.3 V)
• Min. 2.7 V Read Capability
– 160 ns Maximum Access Time
(VCC = 2.7 V)
• 32 Independently Lockable Blocks (16K)
• 100,000 Erase Cycles per Block
• Automated Byte Write/Block Erase
– Command User Interface
– Status Register
– RY /» BY » Status Output
• System Performance Enhancement
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
• Data Protection
– Hardware Erase/Write Lockout during
Power Transition
– Software Erase/Write Lockout
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
• 4 µA (Typ.) ICC in CMOS Standby
• 0.2 µA (Typ.) Deep Power-Down
• State-of-the-Art 0.45 µm ETOX™ Flash
Technology
• Extended Temperature Operation
– -20°C to +85°C
• 49-Pin, .67 mm × 8 mm × 8 mm
CSP Package
49-PIN CSP
TOP VIEW
1234567
A A1 A4 A7 VPP A9 A12 A15
B A2 A5 A17 RP A8 A11 A14
C A3 A6 RY/BY NC WE A10 A13
D A0 DQ9 NC NC NC DQ13 A16
E OE DQ1 DQ3 DQ11 DQ4 DQ6 DAQ-115/
F GND DQ8 DQ10 VCC DQ12 DQ14 GND
G CE DQ0 DQ2 VCC DQ5 DQ7 BYTE
28F400SUB-1
Figure 1. CSP Configuration
1
1 page  
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
When the device power-up or RP » turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP » turns High, Erase All
Unlocked Blocks can be used. If used, Erase is per-
formed with reflecting actual lock status, and after that
Write and Block Erase can be used.
The LH28F400SU contains a Compatible Status
Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory’s Status Register.This reg-
ister, when used alone, provides a straightforward
upgrade capability to the LH28F400SU from a
LH28F008SA-based design.
The LH28F400SU incorporates an open drain
RY »/BY » output pin. This feature allows the user to OR-
tie many RY /» BY » pins together in a multiple memory con-
figuration such as a Resident Flash Array.
The LH28F400SU is specified for a maximum
access time of 150 ns (tACC) at 3.3 V operation (3.0 to
3.6 V) over the extended temperature range (-20 to
+85°C). A corresponding maximum access time of
160 ns (tACC) at 2.7 V (-20 to +85°C) is achieved for
reduced power consumption applications.
The LH28F400SU incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 1 mA at 3.3 V.
A Deep Power-Down mode of operation is invoked
when the RP » (called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power down mode.This mode
brings the device power consumption to less than 8 µA,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP » pin is turned to low in order to
return the device to default configuration. When the
power transition is occurred, or at the power on/off, RP »
is required to stay low in order to protect data from noise.
A recovery time of 750 ns is required from RP » switch-
ing high until outputs are again valid. In the Deep Power-
Down state, the WSM is reset (any current operation
will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE » transitions high and RP » stays high with all input
control pins at CMOS levels. In this mode, the device
draws an ICC standby current of 15 µA.
MEMORY MAP
7FFFFH
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
6C000H
6BFFFH
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
5C000H
5BFFFH
58000H
57FFFH
54000H
53FFFH
50000H
4FFFFH
4C000H
4BFFFH
48000H
47FFFH
44000H
43FFFH
40000H
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
28000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOTE: In Byte-wide (x8) mode A-1 is the lowest order address.
In Word-wide (x16) mode A-1 don't care, address values are
ignored A1.
28F400SUB-3
Figure 3. Memory Map
5
5 Page 
4M (512K × 8, 256K × 16) Flash Memory
LH28F400SUB-Z0
START
WRITE B0H
READ COMPATIBLE
STATUS REGISTER
CSR.7 = 0
1
CSR.6 = 0
1
WRITE FFH
ERASE COMPLETED
READ ARRAY DATA
DONE NO
READING?
YES
WRITE D0H
WRITE FFH
BUS
OPERATION
Write
Read
Standby
COMMAND
COMMENTS
Erase
Suspend
D = B0H
A=X
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Standby
Write
Read
Array
Check CSR.6
1 = Erase Suspended
0 = Erase Completed
D = FFH
A=X
Read
Q = AD
Read must be from
block other than the
one suspended.
Write
Erase
Resume
D = D0H
A=X
See Command Bus Cycle notes for description of codes.
ERASE RESUMED
READ ARRAY DATA
Figure 6. Erase Suspend to Read Array with Compatible Status Register
28F400SUB-6
11
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| PDF Descargar | [ Datasheet LH28F400SUB-Z0.PDF ] | |
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