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Número de pieza | 74AC899 | |
Descripción | 9-Bit Latchable Transceiver | |
Fabricantes | National Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de 74AC899 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
No Preview Available ! August 1994
74AC899 54ACT 74ACT899
9-Bit Latchable Transceiver
with Parity Generator Checker
General Description
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The ’AC ’ACT899 is a 9-bit to 9-bit parity transceiver with
transparent latches The device can operate as a feed-
through transceiver or it can generate check parity from the
8-bit data busses in either direction The ’AC ’ACT899 fea-
tures independent latch enables for the A-to-B direction and
the B-to-A direction a select pin for ODD EVEN parity and
separate error signal output pins for checking parity
Features
Y Latchable transceiver with output sink of 24 mA
Y Option to select generate parity and check or ‘‘feed-
through’’ data parity in directions A-to-B or B-to-A
Y Independent latch enable for A-to-B and B-to-A direc-
tions
Y Select pin for ODD EVEN parity
Y ERRA and ERRB output pins for parity checking
Y Ability to simultaneously generate and check parity
Y May be used in system applications in place of the ’280
Y May be used in system applications in place of the ’657
and ’373 (no need to change T R to check parity)
Y 4 kV minimum ESD immunity
Logic Symbol
Connection Diagram
Pin Assignment for PCC and LCC
TL F 10637 – 1
TL F 10637 – 2
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACTTM is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10637
RRD-B30M75 Printed in U S A
1 page AC Path (Continued)
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O E x BPAR
x(O E
APAR)
xAPAR
ERRA
x(BPAR
ERRB)
ZH HZ
FIGURE 5
FIGURE 6
FIGURE 7
TL F 10637 – 8
TL F 10637 – 9
TL F 10637 – 10
5
5 Page AC Operating Requirements
Symbol
Parameter
VCC
(V)
ts Setup Time HIGH or LOW
An Bn PAR to LEA LEB
th Hold Time HIGH or LOW
An Bn PAR to LEA LEB
tw Pulse Width for LEA LEB
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Voltage Range 5 0 is 5 0V g0 5V
Voltage Range 3 3 is 3 3V g0 3V
33
50
33
50
33
50
74AC
74AC
TA e a25 C
CL e 50 pF
TA e b40 C
to a85 C
CL e 50 pF
Guaranteed Minimum
30 30
30 30
20 20
15 15
40 40
40 40
Units
Fig
No
ns 11 12
ns 11 12
ns 13
AC Electrical Characteristics
Symbol
Parameter
VCC
(V)
tPLH
tPHL
Propagation Delay
An Bn to Bn An
tPLH
tPHL
Propagation Delay
APAR BPAR to BPAR APAR
tPLH
tPHL
Propagation Delay
An Bn to BPAR APAR
tPLH
tPHL
Propagation Delay
An Bn to ERRA ERRB
tPLH
tPHL
Propagation Delay
ODD EVEN to ERRA ERRB
tPLH
tPHL
Propagation Delay
ODD EVEN to APAR BPAR
tPLH
tPHL
Propagation Delay
APAR BPAR to ERRA ERRB
tPLH
tPHL
Propagation Delay
SEL to APAR BPAR
tPLH
tPHL
Propagation Delay
LEB to An Bn
tPLH
tPHL
Propagation Delay
LEA to APAR BPAR
tPLH
tPHL
Propagation Delay
LEA LEB to ERRA ERRB
tPZH
tPZL
Output Enable Time
GBA or GAB to An Bn
tPZH
tPZL
Output Enable Time
GBA or GAB to BPAR or APAR
tPHZ
tPHL
Output Disable Time
GBA or GAB to An Bn
tPHZ
tPLZ
Output Disable Time
GBA or GAB to BPAR APAR
Voltage Range 5 0 is 5 0V g 0 5V
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
74ACT
TA e a25 C
CL e 50 pF
Min Typ Max
2 5 7 5 11 5
15 60 85
2 5 8 5 12 0
2 0 8 0 11 5
2 0 8 0 11 5
2 5 8 0 11 5
1 5 7 5 10 5
15 65 90
2 5 7 0 10 5
2 0 8 0 11 5
2 5 8 0 11 5
2 5 7 0 10 5
15 60 90
15 65 95
15 65 95
54ACT
TA e b55 C
to a125 C
CL e 50 pF
Min Max
1 5 13 5
1 5 11 0
1 5 16 0
1 5 16 0
1 5 16 0
1 5 14 5
1 5 11 5
1 5 12 5
1 5 13 5
1 5 16 0
1 5 16 0
1 5 16 0
1 5 11 0
1 5 11 0
1 5 11 0
74ACT
TA e b40 C
to a85 C
CL e 50 pF
Min Max
Units
Fig
No
2 5 12 0 ns
1
1 5 9 0 ns 1
2 5 12 5 ns
2
2 0 12 0 ns
3
2 0 12 0 ns
4
2 5 12 0 ns
5
1 5 11 5 ns
6
1 5 9 5 ns 9
2 5 11 0 ns 10 11
2 0 12 0 ns 10 11
2 5 12 0 ns 12
2 5 11 0 ns 7 8
1 5 9 5 ns 7 8
1 5 9 5 ns 7 8
1 5 9 5 ns 7 8
11
11 Page |
Páginas | Total 14 Páginas | |
PDF Descargar | [ Datasheet 74AC899.PDF ] |
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74AC899 | 9-Bit Latchable Transceiver | National Semiconductor |
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