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PDF LH28F160SGED-L10 Data sheet ( Hoja de datos )
| Número de pieza | LH28F160SGED-L10 | |
| Descripción | 16 M-bit (512 kB x 16 x 2-Bank) SmartVoltage Dual Work Flash Memory | |
| Fabricantes | Sharp Electrionic Components | |
| Logotipo |  |
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LH28F160SGED-L10
LH28F160SGED-L10
DESCRIPTION
The LH28F160SGED-L10 Dual Work flash memory
with SmartVoltage technology is a high-density,
low-cost, nonvolatile, read/write storage solution for
a wide range of applications. The LH28F160SGED-
L10 is the highest density, highest performance
non-volatile read/write solution for solid-state
storage applications. LH28F160SGED-L10 can
read/write/erase at VCC = 2.7 V and VPP = 2.7 V.
Its low voltage operation capability realizes longer
battery life and suits for cellular phone application.
Its symmetrically-blocked architecture, flexible
voltage and enhanced cycling capability provide for
highly flexible component suitable for resident flash
arrays, SIMMs and memory cards. Its enhanced
suspend capabilities provide for an ideal solution for
code + data storage applications. For secure code
storage applications, such as networking, where
code is either directly executed out of flash or
downloaded to DRAM, the LH28F160SGED-L10
offers three levels of protection : absolute protection
with VPP at GND, selective hardware block locking,
or flexible software block locking. These alternatives
give designers ultimate control of their code security
needs.
FEATURES
• SmartVoltage Dual Work technology
– 2.7 V, 3.3 V or 5 V VCC
– 2.7 V, 3.3 V, 5 V or 12 V VPP
– Capable of performing erase, write and read
for each bank independently (Impossible to
perform read from both banks at a time).
• High performance read access time
– 100 ns (5.0±0.5 V)/100 ns (3.3±0.3 V)/
120 ns (2.7 to 3.6 V)
16 M-bit (512 kB x 16 x 2-Bank)
SmartVoltage Dual Work Flash Memory
• Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Block erase/word write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Thirty-two 32 k-word erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/bank
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases Icc
in static mode
• Automated word write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Package
– 48-pin TSOP Type I (TSOP048-P-1220)
Normal bend
∗ ETOX is a trademark of Intel Corporation.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
1 page  
1 INTRODUCTION
This datasheet contains LH28F160SGED-L10
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F160SGED-
L10 flash memory documentation also includes
ordering information which is referenced in
Section 7.
1.1 New Features
Key enhancements of LH28F160SGED-L10
SmartVoltage Dual Work flash memory are :
• SmartVoltage Dual Work Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
• Permanent Lock Capability
Note following important differences :
• VPPLK has been lowered to 1.5 V to support
3.3 V and 5 V block erase, word write, and lock-
bit configuration operations. Designs that switch
VPP off during read operations should make sure
that the VPP voltage transitions to GND.
• To take advantage of SmartVoltage technology,
allow VCC connection to 2.7 V, 3.3 V or 5 V.
• Once set the permanent lock bit, the blocks
which have been set block lock-bit can not be
erased, written forever.
1.2 Product Overview
The LH28F160SGED-L10 is a high-performance
16 M-bit SmartVoltage Dual Work flash memory
organized as 1 024 k-word of 16 bits. The 1 024 k-
word of data is arranged in thirty-two 32 k-word
blocks which are individually erasable, lockable,
and unlockable in-system. The memory map is
shown in Fig. 1.
All pins except of BE# are shared by both banks,
and BE# is divided to BE0# and BE1# in order to
LH28F160SGED-L10
select one of banks. BE0# is assigned to No. 26
pin which is CE# in LH28F800SGE-L10, BE1#
is assigned to No. 27 pin which is GND in
LH28F800SGE-L10. To select either bank (bank0)
BE0# must be "L", and to select another bank
(bank1) BE1# must be "L". Selecting both banks
(bank0 and bank1) at a time, except of read
operation (array read, status register read), turns
both BE0# and BE1# to "L".
Operation mode of bank0 and bank1 as follows :
1) Both bank0 and bank1 are in deep power-down
(RP# = "L").
2) Both bank0 and bank1 are in standby
(BE0# = BE1# = "H").
3) Bank0 is in standby and bank1 is in active state
of programming or erase, or bank0 is in active
state of programming or erase and bank1 is in
standby.
4) Both bank0 and bank1 are in active state
(impossible to perform simultaneous read from
both banks). In this case bank0 and bank1
perform independent operation, for example,
after input Erase command to bank0 erase or
program command to bank1 is succeeded,
bank0 and bank1 perform each operation
concurrently.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 1, to
meet system performance and power expectations.
2.7 to 3.6 V VCC consumes approximately one-fifth
the power of 5 V VCC. But, 5 V VCC provides the
highest read performance. VPP at 3.3 V and 5 V
eliminates the need for a separate 12 V converter,
while VPP = 12 V maximizes block erase and word
write performance. In addition to flexible erase and
program voltages, the dedicated VPP pin gives
complete data protection when VPP ≤ VPPLK.
-5-
5 Page 
LH28F160SGED-L10
Table 3 Command Definitions (NOTE 9)
COMMAND
BUS CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
REQ’D. NOTE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Array/Reset
1 Write X FFH
Read Identifier Codes
≥2
4 Write
X
90H Read
IA
ID
Read Status Register
2
Write X 70H Read X SRD
Clear Status Register
1
Write X 50H
Block Erase
2 5 Write BA 20H Write BA D0H
Word Write
2
5, 6 Write
WA 40H or 10H Write
WA
WD
Block Erase and
Word Write Suspend
1 5 Write X B0H
Block Erase and
Word Write Resume
1 5 Write X D0H
Set Block Lock-Bit
2
7 Write
BA
60H Write BA
01H
Set Permanent Bank
Lock-Bit
2
7 Write
X
60H Write
X
F1H
Clear Block Lock-Bits
2 8 Write X 60H Write X D0H
NOTES :
1. BUS operations are defined in Table 2.
2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3. SRD = Data read from status register. See Table 6 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or BE# (whichever
goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
permanent lock codes. See Section 4.2 for read
identifier code data.
5. If the block is locked and the permanent lock-bit is not
set, WP# must be at VIH or RP# must be at VHH to
enable block erase or word write operations. Attempts to
issue a block erase or word write to a locked block while
WP# is VIH or RP# is VHH.
6. Either 40H or 10H is recognized by the WSM as the
word write setup.
7. If the permanent bank lock-bit is set, WP# must be at
VIH or RP# must be at VHH to set a block lock-bit. RP#
must be at VHH to set the permanent lock-bit. If the
permanent lock-bit is set, a block lock-bit cannot be set.
Once the permanent lock-bit is set, permanent lock-bit
reset is unable.
8. If the permanent bank lock-bit is set, clear block lock-bits
operation is unable. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the permanent
lock-bit is not set, the Clear Block Lock-Bits command
can be done while WP# is VIH or RP# is VHH.
9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
- 11 -
11 Page | ||
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