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PDF SC411 Data sheet ( Hoja de datos )
| Número de pieza | SC411 | |
| Descripción | Synchronous Buck Pseudo-Fixed Frequency Power Supply Controller | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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SC411
Synchronous Buck Pseudo-Fixed
Frequency Power Supply Controller
POWER MANAGEMENT
Description
Features
The SC411 is a constant on-time synchronous buck PWM
controller in a space-saving MLPQ package intended for
use in notebook computers and other battery operated
portable devices. Features include high efficiency and
a fast dynamic response with no minimum on-time. The
excellent transient response means that SC411 based solu-
tions will require less output capacitance than competing
fixed frequency converters.
www.DataTShheeest4wUi.tccohming frequency is constant until a step-in load or
line voltage occurs. During this time the pulse density and
frequency will increase or decrease to counter the change
in output or input voltage. After the transient event, the
controller frequency will return to steady-state operation.
At light loads, Powersave Mode enables the SC411 to skip
PWM pulses for better efficiency.
The output voltage can be adjusted from 0.5V to VCCA. A
frequency setting resistor sets the on-time for the controller.
The integrated gate drivers feature adaptive shoot-through
protection and soft-switching. Additional features include
cycle-by-cycle current limit, digital soft-start, over-voltage
and under-voltage protection, a Power Good output and
soft discharge upon shutdown.
Constant on-time for fast dynamic response
Programmable VOUT range = 0.5 – VCCA
VBAT range = 1.8V – 25V
DC current sense using low-side RDS(ON)
Sensing or sense resistor
Resistor programmable frequency
Cycle-by-cycle current limit
Digital soft-start
Powersave option
Over-voltage/under-voltage fault protection
10μA typical shutdown current
Low quiescent power dissipation
Power good indicator
1.2% reference
Integrated gate drivers with soft switching
Enable pin
16 pin MLPQ (4mm x 4mm)
Output soft discharge upon shutdown
Applications
Notebook Computers
CPU/IO Supplies
Handheld Terminals and PDAs
LCD Monitors
Network Power Supplies
Typical Application Circuit
VBAT
5VSUS
R1
RTON1
PGOOD
R2
10R U1
R4
C5
1nF
VOUT
C3 R3
1 VOUT
2 VCCA
3 FB
4 PGD
R6
C6
1uF
SC411
5VSUS
VBAT
DH 12
LX 11
ILIM 10
VDDP 9
D1
C1 0.1uF
Q1 C2
10uF
L1
R5
Q2
C7
1uF
C4
+
VOUT
June 2007
1 www.semtech.com
1 page  
SC411
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
Conditions
25°C
-40°C to 125°C
Units
Min Typ Max Min
Max
Soft-Start
Soft-Start Ramp Time
Under-Voltage Blank Time
EN/PSV High to PGD High
EN/PSV High to UV High
440
440
clks(3)
clks(3)
www.DataSGheaette4UD.croimvers
Shoot-Through Delay(4)
DL Pull-Down Resistance
DL Sink Current
DH or DL Rising
DL Low
DL = 2.5V
30
0.80
3.1
ns
1.75 Ω
A
DL Pull-Up Resistance
DL Source Current
DL High
DL = 2.5V
2
1.3
4Ω
A
Notes:
1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC regulation level higher than the
error-comparator threshold by 50% of the ripple voltage.
2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. These values
guaranteed by the ILIM Source Current and Current Comparator Offset tests.
3) clks = Switching cycles.
4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 8.
5) Semtech’s SmartDriverTM FET drive first pulls DH high with a pull-up resistance of 10Ω (typ) until LX = 1.5V (typ). At this point, an additional
pull-up device is activated, reducing the resistance to 2Ω (typ). This negates the need for an external gate or boost resistor.
© 2007 Semtech Corp.
5
www.semtech.com
5 Page 
SC411
POWER MANAGEMENT
Application Information (Cont.)
The current limit circuitry also protects against negative
over-current (i.e. when the current is flowing from the load
to PGND through the inductor and bottom MOSFET). In
this case, when the bottom MOSFET is turned on, the
phase node, LX, will be higher than PGND initially. The
SC411 monitors the voltage at LX, and if it is greater than
a set threshold voltage of 125mV (nom) the bottom MOS-
FET is turned off. The device then waits for approximately
2.5μs and then DL goes high for 300ns (typ) once more
www.DatatSoheseet4nUs.ceomthe current. This repeats until either the over-
current condition goes away or the part latches off due to
output over-voltage (see Output Over-voltage Protection).
Power Good Output
The power good output is an open-drain output and re-
quires a pull-up resistor. When the output voltage is 16%
above or 10% below its set voltage, PGD gets pulled low. It
is held low until the output voltage returns to within these
tolerances once more. PGD is also held low during start-
up and will not be allowed to transition high until soft start
is over (440 switching cycles) and the output reaches 90%
of its set voltage. There is a 5μs delay built into the PGD
circuitry to prevent false transitions.
Output Over-Voltage Protection
resets the fault latch and soft-start counter, and allows
switching to occur if the device is enabled. Switching al-
ways starts with DL to charge up the BST capacitor. With
the soft-start circuit (automatically) enabled, it will pro-
gressively limit the output current (by limiting the current
out of the ILIM pin) over a predetermined time period of
440 switching cycles.
The ramp occurs in four steps:
1) 110 cycles at 25% ILIM with double minimum off-time
(for purposes of the on-time one-shot, there is an internal
positive offset of 120mV to VOUT during this period to aid
in startup).
2) 110 cycles at 50% ILIM with normal minimum off-
time.
3) 110 cycles at 75% ILIM with normal minimum off-time.
4) 110 cycles at 100% ILIM with normal minimum off-
time.
At this point the output under-voltage and power good cir-
cuitry is enabled.
There is 100mV of hysteresis built into the UVLO circuit
and when VCCA falls to 4.1V (nom) the output drivers are
shut down and tri-stated.
When the output exceeds 16% of the its set voltage the
low-side MOSFET is latched on. It stays latched on and
the controller is latched off until reset*. There is a 5μs
delay built into the OV protection circuit to prevent false
transitions.
Output Under-Voltage Protection
When the output is 30% below its set voltage the output
is latched in a tri-stated condition. It stays latched and
the controller is latched off until reset*. There is a 5μs
delay built into the UV protection circuit to prevent false
transitions.
POR, UVLO and Soft-Start
An internal power-on reset (POR) occurs when VCCA ex-
ceeds 3V, starting up the internal biasing. VCCA under-
voltage lockout (UVLO) circuitry inhibits the controller until
VCCA rises above 4.2V. At this time the UVLO circuitry
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moder-
ate-sized high-side, and larger low-side power MOSFETs.
An adaptive dead-time circuit monitors the DL output and
prevents the high-side MOSFET from turning on until DL is
fully off (below ~1V). Semtech’s SmartDriverTM FET drive
first pulls DH high with a pull-up resistance of 10Ω (typ)
until LX = 1.5V (typ). At this point, an additional pull-up
device is activated, reducing the resistance to 2Ω (typ);
This negates the need for an external gate or boost re-
sistor. The adaptive dead time circuit also monitors the
phase node, LX, to determine the state of the high side
MOSFET, and prevents the low side MOSFET from turning
on until DH is fully off (LX below ~1V). Be sure there is
low resistance and low inductance between the DH and
DL outputs to the gate of each MOSFET.
* Note: to reset from any fault, VCCA or EN/PSV must be toggled.
© 2007 Semtech Corp.
11
www.semtech.com
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet SC411.PDF ] | |
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