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PDF SDN8080G Data sheet ( Hoja de datos )

Número de pieza SDN8080G
Descripción 80 COM/SEG Driver
Fabricantes Advanced Semiconductor 
Logotipo Advanced Semiconductor Logotipo



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No Preview Available ! SDN8080G Hoja de datos, Descripción, Manual

DATA SHEET
www.DataSheet4U.com
SDN8080G
80-outputs
common/segment driver
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v6)
2005 Sep 29

1 page




SDN8080G pdf
Avant Electronics
SDN8080G
80-outputs common/segment driver
3.2 Block description
Table 2 Block description
NAME
COM/SEG
Clock control
COM/SEG
Data latch control
SEG
Power down function SEG
Output level selector COM/SEG
www.DataSh2e0etx44U-.bciot m
bi-directional shift
register for
SEGMENT data
SEG
80-bit data latch, or
bi-directional shift
register for
COMMON data
COM/SEG
80-bit level shifter
80-bit 4-level driver
SEG
SEG
DESCRIPTION
Inputs to this block are external signals CL1, CL2, CS, and AMS. It generates
latch clock (LCK) and shift clock (SCK). SCK is used to shift display data into
the 20 x 4-bit bi-directional shift register for SEGMENT data.
This block controls shift direction of the 20 x 4-bit shift register and selects its
input data pins.
In COMMON driver application, this block is disabled.
This block enables or disables Clock Control block according to ERB/ELB
input.
Controls the output voltage level according to input signals M and DISPOFFB.
This is the bi-directional 20 x 4-bit (80-bits) shift register for SEGMEMT data.
In 1-bit serial interface mode of SEGMEN driver application, 80 SCK clocks are
needed to shift in 80-bit data. In 4-bit parallel interface mode, only 20 SCK
clocks are needed to shift in 80-bit data.
In COMMON driver application, this block is disabled.
In SEGMENT driver application, this block is used as an 80-bit data latch and
the 80-bit data of the SEGMENT driver are latched into this latch for output.
In single type COMMON driver application, this block is used as an 80-bit shift
register. Depending on the value of SHL, 1-bit serial data is shifted into D2_DL
or D4_DR.
In dual type COMMON driver application, depending on the value of SHL, the
80-bits shift register is divided into two sections with each section having
40-bits. Data are then shifted into the shift register via D2_DL and D3_DM, or
D3_DM and D4_DR. Please refer to Table 6 and Table 7.
This block translates signals from logical voltage to high voltage for driving the
STN LCD panel.
Selects output voltage levels according to M and the latched data value.
2005 Sep 29
5 of 40
data sheet (v6)

5 Page





SDN8080G arduino
Avant Electronics
SDN8080G
80-outputs common/segment driver
SYMBOL
D1_SID,
D2_DL,
D3_DM,
D4_DR
www.DataSheet4U.com
SHL
ELB, ERB
I/O
I/O,
D2,
D4.
Input,
D1,
D3
input
Interface
to/from
DESCRIPTION
In SEGMENT Driver mode and when 4-bit parallel data interface mode is
selected, these 4 inputs are used as 4-bit parallel data input from a controller.
controller
In SEGMENT driver mode and when 1-bit serial interface mode is selected,
D1_SID is used as serial data input from a controller. In this application, all other 3
inputs must be connected to VDD.
In COMMON driver mode and when single-type application mode is selected,
COMMON scan pulse is shifted from D2_DL to D4_DR or from D4_DR to D2_DL,
depending on the logic state of SHL.
In COMMON driver mode and when dual-type application mode is selected,
COMMON scan pulse is shifted from D2_DL and D3_DM to D4_DR, or from
D4_DR and D3_DM to D2_DL, depending on the logic state of SHL.
Shift direction control.
VDD/VSS
When this input is connected to VSS, data shift direction is from left to right. When
this input is connected to VDD, data shift direction is from right to left. Please refer
to Table 6 and Table 7.
In order to reduce power consumption, in SEGMENTdriver application mode, the
internal operation of the SDN8080G is enabled only when its enable input (ELB or
ERB) is at “LOW”. When several SDN8080G are connected in cascade, their
enable inputs(ELB or ERB) are serially enabled. The enabling sequence is
decided by SHL, as listed below.
input/
output
cascade
SHL
Segment Driver
ELB ERB
L
Output
Input
H
Input
Output
In COMMON driver application, these two pins are not used and should be left
open.
2005 Sep 29
11 of 40
data sheet (v6)

11 Page







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