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PDF LH28F016LL Data sheet ( Hoja de datos )
| Número de pieza | LH28F016LL | |
| Descripción | 16M (1M bb 16/ 2M bb 8) Flash Memory | |
| Fabricantes | Sharp Electrionic Components | |
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LH28F016LL
FEATURES
• User-Configurable x8 or x16 Operation
• 3 V Write/Erase Operation (3 V VPP)
– 2.7 - 3.6 V Write-Erase Operation
• 120 ns Maximum Access Time
(VCC = 3.0 V)
• 150 ns Maximum Access Time
(VCC = 2.7 V)
• 32 Independently Lockable Blocks (64K)
• 0.48 MB/sec Write Transfer Rate
• 100,000 Erase Cycles per Block
• Revolutionary Architecture
– Pipelined Command Execution
– Write During Erase
– Command Superset of
Sharp LH28F016SU
• 10 µA (MAX.) ICC in CMOS Standby
• 5 µA (MAX.) Deep Power-Down
• State-of-the Art 0.6 µm ETOX™
Flash Technology
• 56-Pin, 1.2 mm × 14 mm × 20 mm TSOP
(Type I) Package
16M (1M × 16, 2M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
VSSL
CE1
LX
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
CX
RP
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 WP
55 WE
54 OE
53 RY/BY
52 DQ15
51 DQ7
50 DQ14
49 DQ6
48 GND
47 DQ13
46 DQ5
45 DQ12
44 DQ4
43 VCC
42 GND
41 DQ11
40 DQ3
39 DQ10
38 DQ2
37 VCC
36 DQ9
35 DQ1
34 DQ8
33 DQ0
32 A0
31 BYTE
30 NC
29 NC
28F016LLT-1
Figure 1. TSOP Configuration
1
1 page  
16M (1M × 16, 2M × 8) Flash Memory
LH28F016LL
INTRODUCTION
Sharp’s LH28F016LL 16M Flash Memory is a revo-
lutionary architecture which enables the design of truly
mobile, high performance, personal computing and com-
munication products. With innovative capabilities,
3 V single voltage operation and very high read/write
performance, the LH28F0166LL is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F016LL is very high density, highest per-
formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi-
tecture (100% compatible with the LH28F016SU 16M
Flash memory), extended cycling, minimum power
2.7 V operation, very fast write and read performance
and selective block locking provide a highly flexible
memory component suitable for battery operation por-
table equipment such as digital still camera, PDA, cel-
lular phone, and memory card. Its x8/x16 architecture
allows the optimization of memory to processor inter-
face. The flexible block locking option enables bundling
of executable of executable application software in a
Resident Flash Array or memory card. Manufactured
on Sharp’s 0.6 µm ETOX™ process technology, the
LH28F016LL is the most cost-effective, high-density
3 V single power operation flash memory.
DESCRIPTION
The LH28F016LL is a high performance 16M
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1M × 16 or 2M x 8.
The LH28F016LL includes thirty-two 64K (65,536)
blocks or thirty-two 32-KW (32,768) blocks. A chip
memory map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F016LL:
• 3 V Write/Erase Operation (3 V VPP)
• 3 V Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection
The LH28F016LL will be available in a 56-pin,
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack-
age.This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed us-
ing a Two-Write command sequence to the CUI in the
same way as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Page Buffer Writes to Flash
• Command Queuing Capability
• Automatic Data Writes During Erase
• Software Locking of Memory Blocks
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 9 µs, a 15% improve-
ment over the LH28F008SA.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve 1,000,000 Block
Erase Cycles by providing wear-leveling algorithms and
graceful block retirement. These techniques have
already been employed in many flash file systems and
Hard Disk Drive designs.
The LH28F016LL incorporates two Page Buffers of
256 Bytes (128 Words) each to allow page data writes.
This feature can improve a system write performance
by up to 4.8 times over previous flash memory devices.
All operations are started by a sequence of Write
commands to the device. Three Status Registers (de-
scribed in detail later) and a RY »/BY » output pin provide
information on the progress of the requested operation.
While the LH28F008SA requires an operation to com-
plete before the next operation can be requested, the
LH28F016LL allows queuing of the next operation while
the memory executes the current operation. This elimi-
nates system overhead when writing several bytes in a
row to the array or erasing several blocks at the same
time. The LH28F016LL can also perform write opera-
tions to one block of memory while performing erase of
another block.
The LH28F016LL provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F016LL has a master Write
Protect pin (WP ») which prevents any modifications to
memory blocks whose lock-bits are set.
5
5 Page 
16M (1M × 16, 2M × 8) Flash Memory
LH28F016LL
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 4.1 and 4.2 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Uploaded Status Bits command must be written to reflect the actual
lock-bit status.
3. A0 is automatically complemented to load second byte of data. BY T» E » must be at VIL. A0 value determines which WD/BC is supplied
first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.
5. In x16 mode, only the lower byte DQ0 - DQ7 is used for WCL and WCH. The upper byte DQ8 - DQ15 is a don’t care.
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY »/BY » output to one of two pulse-modes or enable and disable the RY »/BY » function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
LH28F016SU User’s Manual.
10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.
11. Unless you issue erase suspend command, it is not necessary to input D0H on third bus cycle.
Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
76543210
CSR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
CSR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
CSR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
CSR.4 = DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
CSR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
NOTES:
1. RY »/BY » output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of VPP level. The WSM interrogates
VPP’s level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
VPP has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPL and VPPH.
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
11
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