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PDF LH28F008SC-V Data sheet ( Hoja de datos )
| Número de pieza | LH28F008SC-V | |
| Descripción | 8 M-bit (1 MB x 8) Smart 5 | |
| Fabricantes | Sharp Electrionic Components | |
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LH28F008SC-V/SCH-V
LH28F008SC-V/SCH-V
8 M-bit (1 MB x 8) Smart 5
Flash Memories
DESCRIPTION
The LH28F008SC-V/SCH-V flash memories with
Smart 5 technology are high-density, low-cost,
nonvolatile, read/write storage solution for a wide
range of applications. Their symmetrically-blocked
architecture, flexible voltage and enhanced cycling
capability provide for highly flexible component
suitable for resident flash arrays, SIMMs and memory
cards. Their enhanced suspend capabilities provide
for an ideal solution for code + data storage
applications. For secure code storage applications,
such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the
LH28F008SC-V/SCH-V offer three levels of
protection : absolute protection with VPP at GND,
selective hardware block locking, or flexible software
block locking. These alternatives give designers
ultimate control of their code security needs.
FEATURES
• Smart 5 technology
– 5 V VCC
– 5 V or 12 V VPP
• High performance read access time
LH28F008SC-V85/SCH-V85
– 85 ns (5.0±0.25 V)/90 ns (5.0±0.5 V)
LH28F008SC-V12/SCH-V12
– 120 ns (5.0±0.5 V)
• Enhanced automated suspend options
– Byte write suspend to read
– Block erase suspend to byte write
– Block erase suspend to read
• Enhanced data protection features
– Absolute protection with VPP = GND
– Flexible block locking
– Block erase/byte write lockout during power
transitions
• SRAM-compatible write interface
• High-density symmetrically-blocked architecture
– Sixteen 64 k-byte erasable blocks
• Enhanced cycling capability
– 100 000 block erase cycles
– 1.6 million block erase cycles/chip
• Low power management
– Deep power-down mode
– Automatic power saving mode decreases ICC
in static mode
• Automated byte write and block erase
– Command user interface
– Status register
• ETOXTM∗ V nonvolatile flash technology
• Packages
– 40-pin TSOP Type I (TSOP040-P-1020)
Normal bend/Reverse bend
– 44-pin SOP (SOP044-P-0600)
– 48-ball CSP (FBGA048-P-0608)
∗ ETOX is a trademark of Intel Corporation.
COMPARISON TABLE
VERSIONS
OPERATING TEMPERATURE
LH28F008SC-V
LH28F008SCH-V
0 to +70˚C
–25 to +85˚C
DC CHARACTERISTICS
VCC deep power-down current (MAX.)
10 µA
20 µA
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books,
etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
-1-
1 page  
1 INTRODUCTION
This datasheet contains LH28F008SC-V/SCH-V
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications. LH28F008SC-V/
SCH-V flash memories documentation also
includes ordering information which is referenced in
Section 7.
1.1 New Features
LH28F008SC-V/SCH-V Smart 5 flash memories
maintain backwards-compatibility with the
LH28F008SA. Key enhancements over the
LH28F008SA include :
• Smart 5 Technology
• Enhanced Suspend Capabilities
• In-System Block Locking
Both devices share a compatible pinout, status
register, and software command set. These
similarities enable a clean upgrade from the
LH28F008SA to LH28F008SC-V/SCH-V. When
upgrading, it is important to note the following
differences :
• Because of new feature support, the two
devices have different device codes. This
allows for software optimization.
• VPPLK has been lowered from 6.5 V to 1.5 V to
support 5 V block erase, byte write, and lock-bit
configuration operations. Designs that switch
VPP off during read operations should make
sure that the VPP voltage transitions to GND.
• To take advantage of Smart 5 technology, allow
VPP connection to 5 V.
1.2 Product Overview
The LH28F008SC-V/SCH-V are high-performance
8 M-bit Smart 5 flash memories organized as 1 M-
byte of 8 bits. The 1 M-byte of data is arranged in
sixteen 64 k-byte blocks which are individually
LH28F008SC-V/SCH-V
erasable, lockable, and unlockable in-system. The
memory map is shown in Fig.1.
Smart 5 technology provides a choice of VCC and
VPP combinations, as shown in Table 1, to meet
system performance and power expectations. VPP
at 5 V eliminates the need for a separate 12 V
converter, while VPP = 12 V maximizes block erase
and byte write performance. In addition to flexible
erase and program voltages, the dedicated VPP pin
gives complete data protection when VPP ≤ VPPLK.
Table 1 VCC and VPP Voltage Combinations
Offered by Smart 5 Technology
VCC VOLTAGE
5V
VPP VOLTAGE
5 V, 12 V
Internal VCC and VPP detection circuitry auto-
matically configures the device for optimized read
and write operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, byte write, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64 k-byte blocks typically within 1 second (5 V VCC,
12 V VPP) independent of other blocks. Each block
can be independently erased 100 000 times (1.6
million block erases per device). Block erase
suspend mode allows system software to suspend
block erase to read data from, or write data to any
other block.
Writing memory data is performed in byte
increments typically within 6 µs (5 V VCC, 12 V
VPP). Byte write suspend mode enables the system
-5-
5 Page 
LH28F008SC-V/SCH-V
Table 3 Command Definitions (NOTE 9)
COMMAND
BUS CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
REQ’D.
NOTE Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3) Oper (NOTE 1) Addr (NOTE 2) Data (NOTE 3)
Read Array/Reset
1
Write
X
FFH
Read Identifier Codes
≥2
4 Write
X
90H Read
IA
ID
Read Status Register
2
Write
X
70H Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
5 Write
BA
20H Write
BA
D0H
Byte Write
2
5, 6 Write
WA 40H or 10H Write
WA
WD
Block Erase and
Byte Write Suspend
1
5 Write
X
B0H
Block Erase and
Byte Write Resume
1
5 Write
X
D0H
Set Block Lock-Bit
2
7 Write
BA
60H Write
BA
01H
Set Master Lock-Bit
2
7 Write
X
60H Write
X
F1H
Clear Block Lock-Bits
2
8 Write
X
60H Write
X
D0H
NOTES :
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased or locked.
WA = Address of memory location to be written.
3. SRD = Data read from status register. See Table 6 for a
description of the status register bits.
WD = Data to be written at location WA. Data is latched
on the rising edge of WE# or CE# (whichever
goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read
operations access manufacture, device, block lock, and
master lock codes. See Section 4.2 for read identifier
code data.
5. If the block is locked, RP# must be at VHH to enable
block erase or byte write operations. Attempts to issue a
block erase or byte write to a locked block while RP# is
VIH.
6. Either 40H or 10H is recognized by the WSM as the
byte write setup.
7. If the master lock-bit is set, RP# must be at VHH to set a
block lock-bit. RP# must be at VHH to set the master
lock-bit. If the master lock-bit is not set, a block lock-bit
can be set while RP# is VIH.
8. If the master lock-bit is set, RP# must be at VHH to clear
block lock-bits. The clear block lock-bits operation
simultaneously clears all block lock-bits. If the master
lock-bit is not set, the Clear Block Lock-Bits command
can be done while RP# is VIH.
9. Commands other than those shown above are reserved
by SHARP for future device implementations and should
not be used.
- 11 -
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