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PDF T2316407A Data sheet ( Hoja de datos )
| Número de pieza | T2316407A | |
| Descripción | (T2316405A / T2316407A) EDO/FPM DRAM | |
| Fabricantes | Taiwan Memory Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de T2316407A (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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tm TE
CH
DRAM
FEATURES
• Industry-standard x 4 pinouts and timing
functions
• power supply : T2316405A 2.6V(±0.2V)
www.DataSheet4U.com
T2316407A 3.3V(±0.3V)
• All device pins are TTL- compatible.
• 2048-cycle refresh in 32 ms.
• Refresh modes: RAS only, CAS BEFORE
RAS (CBR) and HIDDEN.
• Extended data-out (EDO) PAGE MODE
access cycle.
OPTION
TIMING
50ns (For T2316407A only)
60ns (For T2316407A only)
70ns (For T2316407A only)
100ns (For T2316405A only)
MARKING
-50
-60
-70
-10
PACKAGE
26/24-pin SOJ
26/24-pin TSOP-II
J
S
PIN ARRANGEMENT (Top View)
Vcc
I/O1
I/O2
WE
RAS
NC
1
2
3
4
5
6
A10 8
A0 9
A1 10
A2 11
A3 12
Vcc 13
SOJ
&
TSOP-II
26 Vss
25 I/O4
24 I/O3
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 Vss
T2316405A
Preliminary T2316407A
4M x 4 DYNAMIC RAM
EDO PAGE MODE
GRNERAL DESCRIPTION
The T2316405A and T2316407A is a randomly
accessed solid state memory containing 16,777,216
bits organized in a x 4 configuration. It offers Fast
Page mode with Extended Data Output (EDO).
During READ or WRITE cycles, each of the 4
memory bits (1 bit per I/O) is uniquely addressed
through the 22 address bits, which are entered 11
bits (A0-A10) at a time. RAS latches the first 11
bits and CAS latches the latter 11 bits.
A READ or WRITE cycle is selected with
the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates
WRITE mode. During a WRITE cycle, data -in is
latched by the falling edge of WE or CAS ,
whichever occurs last. When WE goes Low prior
to CAS going LOW ( EARLY WRITE cycle), the
output pins remain open (High-Z) until the next
CAS cycle.
A Late Write or Read-Modify-Write occurs.
When WE falls after CAS was taken LOW (Late
Write cycle). OE must be taken HIGH to disable
the data-outputs prior to applying input data.
The four data inputs and four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by WE and OE .
Taiwan Memory Technology, Inc. reserves the right P. 1
to change products or specifications without notice.
Publication Date: APR 2001
Revision:0.B
1 page  
tm TE
CH
T2316405A
Preliminary T2316407A
AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70°C)
TEST CONDITIONS:
T2316405A-10 Vcc = 2.6V ± 0.2V , T2316407A-50/60/70 Vcc = 3.3V ± 0.3V
VIH/VIL=2.0/0.8V,VOH/VOL=2.0/0.8V
Input rise and fall times: 2ns , Output Load: 2TTL gate + CL (100pF)
AC CHARACTERISTICS
PARAMETER
Read or Write Cycle Time
Read Write Cycle Time
www.DataSheet4U.comEDO-Page-Mode Read or Write Cycle Time
EDO-Page-Mode Read-Write Cycle Time
Access Time From RAS
Access Time From CAS
Access Time From OE
Access Time From Column Address
Access Time From CAS Precharge
RAS Pulse Width
RAS Pulse Width (EDO Page Mode)
RAS Hold Time
RAS Precharge Time
CAS Pulse Width
CAS Hold Time
CAS Precharge Time (EDO Page Mode)
RAS to CAS Delay Time
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
RAS to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference to
RAS )
Column Address to RAS Lead Time
Read Command Setup Time
Read Command Hold Time Reference to
CAS
Read Command Hold Time Reference to
RAS
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or
RAS
SYM -50 -60 -70 -10 UNIT Notes
Min Max Min Max Min Max Min Max
tRC 84
104 124 180
ns
tRWC 108 135 160 240
ns
tPC 20 25 30 40 ns
tPCM 56 68 78 120 ns
tRAC 50 60 70 100 ns 4
tCAC 13 15 20 25 ns 5
tOAC 13 15 20 25 ns 13
tAA 25 30 35 50 ns 8
tACP 30 35 40 55 ns
tRAS 50 10K 60 10K 70 10K 100 10K ns
tRASC
50
100
K
60
100
K
70
100
K
100
100
K
ns
tRSH 8
10 13
25 ns
tRP 30 40 50 70 ns
tCAS 8 10K 10 10K 13 10K 25 10K ns
tCSH 38 40 45 100 ns
tCP 10 10 10 10 ns
tRCD 12 37 14 45 14 50 25 75 ns 7
tCRP 5 5 5 5 ns
tASR 0 0 0 0 ns
tRAH 8
10 10 15
ns
tRAD 10 25 12 30 12 35 20 50 ns 8
tASC 0 0 0 0 ns
tCAH 8
10 13
20 ns
tAR 21 24 27 45 ns
tRAL 25 30 35 50 ns
tRCS 0 0 0 0 ns 14
tRCH 0 0 0 0 ns 9,14
tRRH 0
0
0
9
0 ns
tCLZ 0 0 0 0 ns
tOFF1
0
12
0
15 0
20
0
10,16
25 ns
Taiwan Memory Technology, Inc. reserves the right P. 5
to change products or specifications without notice.
Publication Date: APR. 2001
Revision:0.B
5 Page 
tm TE
CH
T2316405A
Preliminary T2316407A
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
RAS VVIIHL
www.DataSheet4U.com
CA S VVIIHL
ADDR VVIIHL
WE VVIIHL
I/O VVIIOOHL
OE VVIIHL
tR A SC
tCRP
tC S H
tR C D
t PC
tCAS
tCP
tC A S
t PC
tC P
tR SH
tC A S
tR A D
tA S R t R A H
ROW
tA R
t AS C
tC A H
C OLU M N(A)
tR C S
tA S C tC A H
C OLUMN(B )
tR C H
tR A L
t AS C tC A H
C O L U M N (N )
tW C S
tWC H
tA A
t R AC
tCAC
O PE N
tOA C
tA C P
tA A
tC A C
tC O H
V A L ID D A T A ( A )
t WHZ
V A L ID
DA T A (B )
tDS tDH
VALID DATA
IN
tRP
tCP
ROW
RAS
VVII
H
L
CA S
VVII
H
L
A D DR
VVII
H
L
I /O
V
V
OH
OL
RAS ONLY REFRESH CYCLE
(ADDR=A0-A10;O E , W E =DON‘T CARE)
tCRP
tASR
tR A H
ROW
tR A S
t RC
tR P
tR PC
OP EN
RO W
DON'T CARE
UNDEFINED
2Taiwan Memory Technology, Inc. reserves the right P. 11
to change products or specifications without notice.
Publication Date: APR. 2001
Revision:0.B
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet T2316407A.PDF ] | |
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