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PDF LH28F004SU-Z9 Data sheet ( Hoja de datos )
| Número de pieza | LH28F004SU-Z9 | |
| Descripción | 4M (512 bb 8) Flash Memory | |
| Fabricantes | Sharp Electrionic Components | |
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LH28F004SU-Z9
4M (512 × 8) Flash Memory
FEATURES
• 512K × 8 Word Configuration
• 2.7 V Write/Erase Operation (5 V ± 0.5 V
VPP, 3.0 V ± 0.3 V VCC, +15°C to +35°C)
– No Requirement For DC/DC Converter
To Write/Erase
• 150 ns Maximum Access Time
(VCC = 3.3 V ± 0.3 V)
• Minimum 2.7 V Read Capability
– 190 ns Maximum Access Time
(VCC = 2.7 V, -20°C to +85°C)
– 180 ns Maximum Access Time
(VCC = 2.7 V, 0°C to +70°C)
• 32 Independently Lockable Blocks (16K)
• 100,000 Erase Cycles per Block
• Automated Byte Write/Block Erase
– Command User Interface
– Status Register
– RY /» BY » Status Output
• System Performance Enhancement
– Erase Suspend For Read
– Two-Byte Write
– Full Chip Erase
• Data Protection
– Hardware Erase/Write Lockout During
Power Transitions
– Software Erase/Write Lockout
• Independently Lockable For Write/Erase
On Each Block (Lock Block and Protect
Set/Reset)
• 4 µA (Typ.) ICC In CMOS Standby
• 0.2 µA (Typ.) Deep Power-Down
• State-of-the-Art 0.45 µm ETOX™
Flash Technology
• Extended Temperature Operation
– -20°C to +85°C (Read)
– +15°C to +35°C (Write/Erase)
• 42-pin, 0.67 mm × 8 mm × 8 mm
CSP Package
42-PIN CSP
TOP VIEW
1234567
A GND DQ6 VCC VCC DQ2 OE GND
B A17 DQ7 DQ4 NC NC DQ0 CE
C A10 NC DQ5 NC DQ3 DQ1 A0
D A14 A13 A9 NC RY/BY A6 A3
E A16 A11 WE RP A7 A4 A1
F A15 A12 A8 VPP A18 A5
A2
28F004SU-Z9 -1
Figure 1. CSP Configuration
INTRODUCTION
Sharp’s LH28F004SU 4M Flash Memory is a revolu-
tionary architecture which enables the design of truly
mobile, high performance, personal computing and
communication products. With innovative capabilities,
3.3 V low power operation and very high read/write
performance, the LH28F004SU is also the ideal choice
for designing embedded mass storage flash memory
systems.
The LH28F004SU’s independently lockable 32 sym-
metrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsimile, game, PC, printer and handy terminal. The
LH28F004SU’s 5.0 V/3.3 V power supply operation
enables the design of memory cards which can be read
in 3.3 V system and written in 5.0 V/3.3 V systems. Its
x8 architecture allows the optimization of memory to
processor interface. The flexible block locking option
enables bundling of executable application software in
a Resident Flash Array or memory card. Manufactured
on Sharp’s 0.45 µm ETOX™ process technology, the
LH28F004SU is the most cost-effective, high-density
3.3 V flash memory.
1
1 page  
4M (512K × 8) Flash Memory
LH28F004SU-Z9
The LH28F004SU contains a Compatible Status
Register (CSR) which is 100% compatible with the
LH28F008SA Flash memory’s Status Register.This reg-
ister, when used alone, provides a straightforward
upgrade capability to the LH28F004SU from a
LH28F008SA based design.
The LH28F004SU incorporates an open drain
RY »/BY » output pin. This feature allows the user to or-tie
many RY »/BY » pins together in a multiple memory con-
figuration such as a Resident Flash Array.
The LH28F004SU is specified for a maximum
access time of 150 ns (tACC) at 3.3 V operation (3.0 to
3.6 V) over the commercial temperature range (-20 to
+85°C). A corresponding maximum access time of
190 ns (tACC) at 2.7 V (-20 to +85°C) and 180 ns (tACC)
at 2.7 V (0 to +70°C) is achieved for reduced power
consumption applications.
The LH28F004SU incorporates an Automatic Power
Saving (APS) feature which substantially reduces the
active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 1 mA at 3.3 V.
A Deep Power-Down mode of operation in invoked
when the RP » (called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power down mode.This mode
brings the device power consumption to less than 8 µa,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP » pin is turned to low in order to
return the device to default configuration. When the
power transition has occurred, or at the power on/off,
RP » is required to stay low in order to protect data from
noise. A recovery time of 750 ns is required from RP »
switching high until outputs are again valid. In the Deep
Power-Down state, the WSM is reset (any current op-
eration will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE » transitions high and RP » stays high with all input
control pins at CMOS levels. In this mode, the device
draws an ICC standby current of 15 µA.
BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS
Bus Operations
MODE
RP » CE » OE » WE A0 DQ0-7 RY »/BY» NOTE
Read
VIH VIL VIL VIH
X DOUT
X 1, 2, 7
Output Disable
VIH VIL VIH VIH
X High-Z X 1, 6, 7
Standby
VIH VIH
X
X
X High-Z X 1, 6, 7
Deep Power-Down VIL
X
X
X
X High-Z VOH
1, 3
Manufacturer ID
VIH VIL VIL VIH VIL B0H VOH
4
Device ID
VIH VIL VIL VIH VIH
ID
VOH
4
Write
VIH VIL VIH VIL X DIN
X 1, 5, 6
NOTES:
1. X can be VIH or VIL for address or control pins except for RY »/BY », which is either VOL or VOH.
2. RY »/BY » output is open drain. When the WSM is ready, Erase is suspended or the device is in deep
power-down mode, RY »/BY » will be at VOH if it is tied to VCC through a resistor. When the RY /» BY »
at VOL is independent of OE » while a WSM operation is in progress.
3. RP » at GND ± 0.2 V ensures the lowest deep power-down current.
4. A0 at VIL provide manufacturer ID codes. A0 at VIH provide device ID codes. Device ID code= 23H.
All other addresses are set to zero.
5. Commands for different Erase operations, Data Write operations, and Lock-Block operations can only
be successfully completed when VPP = VPPH.
6. While the WSM is running, RY »/BY » in Level-Mode (default) stays at VOL until all operations are complete.
RY »/BY » goes to VOH when the WSM is not busy or in erase suspend mode.
7. RY »/BY may be at VOL while the WSM is busy performing various operations. For example, a status register
read during a write operation.
5
5 Page 
4M (512K × 8) Flash Memory
LH28F004SU-Z9
START
READ COMPATIBLE
STATUS REGISTER
CSR.7 = 0
1
RESET WP
READ COMPATIBLE
STATUS REGISTER
CSR.7 = 0
1
WRITE 77H
WRITE D0H AND
BLOCK ADDRESS
READ COMPATIBLE
STATUS REGISTER
0
CSR.7 =
BUS
OPERATION
COMMAND
COMMENTS
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
Reset
After Write D = 47H A = X,
Write Protect Write D = D0H A = 0FFH
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
Lock Block D = 77H
A=X
Write
Confirm
D = D0H
A = BA
Read
Q = CSRD
Toggle CE or OE
to update CSRD.
1 = WSM Ready
0 = WSM Busy
Write
Set After Write D = 57H A = X,
Write Protect Write D = D0H A = 0FFH
NOTE:
See CSR Full Status Check for Data-Write operation.
If CSR.4, 5 is set, as it is command sequence error,
should be cleared before further attempts are initiated.
Write FFH after the last operation to reset device to read
array mode.
See Command Bus Definitions for description of codes.
1
1 (NOTE)
CSR.4, 5 =
0
LOCK
ANOTHER
YES
BLOCK?
NO
SET WP
OPERATION COMPLETE
Figure 7. Block Locking Scheme
28F004SU-Z9-7
11
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| PDF Descargar | [ Datasheet LH28F004SU-Z9.PDF ] | |
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