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PDF IDT74ALVCH16903 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVCH16903 | |
| Descripción | 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER | |
| Fabricantes | Integrated Device Technology | |
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IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 12-BIT UNIVERSAL
BUS DRIVER WITH PARITY
CHECKER, DUAL 3-STATE
OUTPUTS AND BUS-HOLD
IDT74ALVCH16903
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
www.Data•ShVeCeCt4=U.2c.o5mV ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +4.6
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5
(Outputs Only)
TSTG Storage Temperature
–65 to +150
IOUT DC Output Current
–50 to +50
IIK Continuous Clamp Current,
VI < 0 or VI > VCC
±50
IOK Continuous Clamp Current, VO < 0
–50
ICC Continuous Current through each
ISS VCC or GND
±100
Unit
V
V
°C
mA
mA
mA
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. This value is limited to 4.6V maximum.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT
Output Capacitance VOUT = 0V
7
9 pF
COUT
I/O Port Capacitance VIN = 0V
7
9 pF
NOTE:
1. As applicable to the device type.
DESCRIPTION:
This 12-bit universal bus driver is built using advanced dual metal CMOS
technology. This device has dual outputs and can operate as a buffer or an
edge-triggered register. In both modes, parity is checked on APAR, which
arrives one cycle after the data to which it applies. The YERR output, which is
produced one cycle after APAR, is open drain.
MODE selects one of the two data paths. When MODE is low, the device
operates as an edge-triggered register. On the positive transition of the clock
(CLK) input and when the clock-enable (CLKEN) input is low, data setup at the
A inputs is stored in the internal registers. On the positive transition of CLK and
when CLKEN is high, only data setup at the 9A-12A inputs is stored in their
internal registers. When MODE is high, the device operates as a buffer and data
attheAinputspassesdirectlytotheoutputs.The11A/YERREN servesadual
purpose;itactsasanormaldatabitandalsoenables YERR datatobeclocked
into the YERR output register.
When used as a single device, parity output enable (PAROE) must be tied
high; when parity input/output (PARI/O) is low, even parity is selected and when
PARI/O is high, odd parity is selected. When used in pairs and PAROE is low,
the parity sum is output on PARI/O for cascading to the second ALVCH16903.
When used in pairs and PAROE is high, PARI/O accepts a partial parity sum
from the first ALVCH16903.
A buffered output-enable (OE) input can be used to place the 24 outputs and
YERR in either a normal logic state (high or low logic levels) or a high-impedance
state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the
capability to drive bus lines without need for interface or pullup components.
The ALVCH16903 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16903 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high-impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
JANUARY 2004
DSC-4911/2
1 page  
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS, xYx PORTS
Symbol
Parameter
Test Conditions(1)
Min. Max. Unit
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 6mA, VIH = 1.7V
2
—
VOH Output HIGH Voltage
VCC = 2.3V
IOH = – 12mA, VIH = 1.7V
1.7
—V
VCC = 2.7V
IOH = – 12mA, VIH = 2V
2.2
—
VCC = 3V
2.4 —
VCC = 3V
IOH = – 24mA, VIH = 2V
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
— 0.2
VOL Output LOW Voltage
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VCC = 2.3V
VCC = 2.7V
IOL = 6mA, VIL = 0.7V
IOL = 12mA, VIL = 0.7V
IOL = 12mA, VIL = 0.8V
—
—
—
0.4
0.7 V
0.4
VCC = 3V
IOL = 24mA, VIL = 0.8V — 0.55
IOH High-Level Output Current
VCC = 2.3V
VCC = 2.7V
VCC = 3V
VCC = 2.3V
Y Port
PARI/O
Y Port
Y Port
— −12
— −12 mA
— −12
— −24
— 12
IOL Low-Level Output Current
VCC = 2.7V
VCC = 3V
PARI/O
Y Port
— 12
— 12 mA
— 24
YERR Output
— 24
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS FOR YERR AND PARI/O
Symbol
Parameter
Test Conditions(1)
Min.
VOH PARI/O
VCC = 3V
IOH = – 12mA, VIH = 2V
2
VOL PARI/O
VCC = 3V
IOL = 12mA, VIL = 0.8V
—
Max. Unit
—V
0.55 V
VOL YERR Output only
VCC = 3V
IOL = 24mA
— 0.5 V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
5
5 Page 
IDT74ALVCH16903
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ± 0.2V
From Output
Under Test
CL = 30 pF
(see Note 1)
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500Ω
500Ω
Load Circuit
2 x VCC
S1 Open
GND
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 x VCC
GND
YERR
tPHL (see Note 8)
tPLH (see Note 9)
S1
2 x VCC
2 x VCC
T IM IN G
INPUT
DATA
INPUT
VCC/2
tsu
VCC/2
th
V CC/2
Voltage Waveforms
Setup and Hold Times
VCC
0V
VCC
0V
IN P U T
tW
V CC/2
Voltage Waveforms
Pulse Duration
V C C /2
VCC
0V
Input
tPLH
Output
Vcc /2
Vcc /2
Vcc
Vcc /2
0V
tPHL
VOH
Vcc /2
VOL
Voltage Waveforms
Propagation Delay Times
INPUT
CONTROL
(low-level
enabling)
tPZL
OUTPUT
WAVEFORM 1
S1 at 2xVcc
(see Note 2)
OUTPUT
WAVEFORM 2
S1 at GND
(see Note 2)
VCC/2
Vcc/2
tPZH
V cc/2
VCC/2
VCC
0V
tPLZ
VCC
VOL+0.15V
VOL
tPHZ
VOH
VOH-0.15V
0V
Voltage Waveforms
Enable and DisableTimes
NOTES:
1. CL includes probe and jig capacitance.
2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50Ω, tr ≤ 2 ns, tf ≤ 2 ns.
4. The outputs are measured one at a time with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis.
6. tPZL and tPZH are the same as ten.
7. tPLH and tPHL are the same as tpd.
8. tPHL is measured at VCC /2.
9. tPLH is measured at VOL + 0.15V.
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVCH16903.PDF ] | |
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