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PDF IDT74ALVCH16901 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVCH16901 | |
| Descripción | 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 18-BIT
IDT74ALVCH16901
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
www.Data•ShVeCeCt4=U.2c.o5mV ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses in
either direction.
The ALVCH16901 features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and ERRB) outputs
for checking parity. The direction of data flow is controlled by OEAB and
OEBA. When SELis low, the parity functions are enabled. When SEL is high,
the parity functions are disabled and the device acts as an 18-bit registered
transceiver.
The ALVCH16901 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16901 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
LEAB 2
1CLKENAB
2CLKENAB
CLKAB
OEAB
1
32
3
30
2
35 OEBA
1A1-1A8
1APAR
1ERRB
2A1-2A8
2APAR
2ERRB
5
61
28
36
ODD/EVEN
SEL
34
31
A-Port
Parity
Generate
and
Check
B Data
18
18-Bit
18
Storage QA
18 18-Bit
QB Storage
18
B-Port
Parity
Generate
and
Check
A Data
2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©2000 Integrated Device Technology, Inc.
1
1B1-1B8
60 1BPAR
4 1ERRA
2B1-2A8
37
2BPAR
29
2ERRA
62 CLKBA
64 1CLKENBA
33 2CLKENBA
63 LEBA
JUNE 2000
DSC-4582/1
1 page  
IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VOH Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
VCC = 2.3V
IOH = – 12mA
VCC = 2.7V
VCC = 3V
VCC = 3V
IOH = – 24mA
VOL OutputLOWVoltage
VCC = 2.3V to 3.6V
IOL = 0.1mA
VCC = 2.3V
IOL = 6mA
www.DataSheet4U.com
VCC = 2.7V
IOL = 12mA
IOL = 12mA
VCC = 3V
IOL = 24mA
Min. Max. Unit
VCC – 0.2
—
V
2—
1.7 —
2.2 —
2.4 —
2—
— 0.2 V
— 0.4
— 0.7
— 0.4
— 0.55
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
CPD
CPD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
VCC = 2.5V ± 0.2V
Typical
22
5
VCC = 3.3V ± 0.3V
Typical
27
8
Unit
pF
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVCH16901.PDF ] | |
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