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PDF IDT74ALVCH162827 Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVCH162827 | |
| Descripción | 3.3V CMOS 20-BIT BUFFER/ DRIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74ALVCH162827
3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
3.3V CMOS 20-BIT BUFFER/
DRIVER WITH 3-STATE
OUTPUTS AND BUS-HOLD
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH162827
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
www.Data•ShVeCeCt4=U.2c.o5mV ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
DESCRIPTION:
This 20-bit buffer/driver is built using advanced dual metal CMOS technology.
The ALVCH162827 device provides high-performance bus interface buffering
for wide data/address paths or busses carrying parity. Two pairs of NAND-ed
output enable controls offer maximum control flexibility and are organized to
operate the device as two 10-bit buffers or one 20-bit buffer. Flow-through
organization of signal pins facilitates ease of layout. All inputs are designed with
hysteresis for improved noise margin.
The ALVCH162827 has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been designed to drive ±12mA at the designated threshold levels.
The ALVCH162827 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OE1
1OE2
1
56
1A1 55
2OE1
2OE2
28
29
2 1Y1
2A1 42
15 2Y1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©2003 Integrated Device Technology, Inc.
1
OCTOBER 2003
DSC-4567/3
1 page  
IDT74ALVCH162827
3.3V CMOS 20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
www.DataSheet4U.com
VCC
Pulse(1, 2)
Generator
VIN
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC Link
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VLOAD/2
VT
tPHZ
VT
0V
VIH
VT
0V
VLOAD/2
VLZ
VOL
VOH
VHZ
0V
ALVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
tSU tH
tREM
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU tH
VIH
VT
0V
ALVC Link
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
ALVC Link
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVCH162827.PDF ] | |
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